An electronic circuit card comprises a printed circuit board (PCB) with electronic components thereon. The electronic components comprise drivers for transmitting TX signals and receivers for receiving RX signals, according to several groups of interface signals. There is further provided a connector edge, arranged at an edge of the card, and configured to allow the card to be connected to an external connector. This connector edge comprises two subsets of symmetric pins on respective (opposite) sides thereof. The drivers and the receivers are connected to the pins, for respectively conveying the TX signals and the RX signals. Pins are assigned such that, for each of the several groups of supported interface signals, any pin (of any of the subsets) connected to transmit TX signals is located opposite a pin (of the other subset) connected to receive RX signals. Pairs of consecutive pins (on each side) typically come in differential pairs.

A circuit board includes a first substrate, a second substrate, a third substrate, a plurality of conductive structures and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fully fills the opening. The conductive via structure penetrates the first substrate, the second substrate, the third dielectric layer of the third substrate, and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.

A hermetically sealed filtered feedthrough for an active implantable medical device includes a first conductive leadwire extending from a first end to a second end, the first leadwire second end extending outwardly beyond the device side of an insulator hermetically sealed to a ferrule for the feedthrough. A circuit board supporting a chip capacitor is disposed adjacent to a device side of the insulator and has a circuit board passageway. The first leadwire first end resides in the circuit board passageway. A second conductive leadwire on the device side has a second leadwire first end disposed in the circuit board passageway with a second leadwire second end extending outwardly beyond the circuit board to be connectable to AIMD internal electronics. The second leadwire first end is connected to the first leadwire first end and a capacitor internal metallization in the circuit board passageway. The circuit board further comprises a ground electrode plate that is connected to the ground termination of the chip capacitor and to the ferrule.

A multilayer substrate includes a multilayer body, an internal wire, land electrodes, and a ground electrode. The internal wire extends toward the land electrode from a position where the internal wire overlaps the land electrode when viewed from a first surface and is electrically connected to the land electrode by a via conductor. The internal wire is electrically connected to the ground electrode by a via conductor that is provided in a region from a position where a capacitor is located where the via conductor at least partially overlaps the land electrode when viewed from the first surface.

The present invention addresses providing an electromagnetic wave reducing structure that can reduce leakage to outside of noise that is emitted by a circuit, from low frequency to high frequency, without using a special, difficult to obtain item. To address this problem, the electromagnetic wave reducing structure is provided with: a first conductor layer and a second conductor layer facing opposite each other; and a capacitor group comprising a plurality of capacitors connected to the first conductor layer and the second conductor layer. All the gaps are approximately equal between the capacitors in any pair of adjacent capacitors in a first direction within the plane and any pair of adjacent capacitors in a second direction which is the direction within the plane that is approximately perpendicular to the first direction, in a surface parallel to the surface of the first conductor layer that faces opposite the second conductor layer.

In one embodiment, an apparatus includes first and second via structures in a substrate. Each via structure defines a coupling element that extends from the via structure toward the other via structure such that the coupling elements capacitively couple with one another in an area between the first and second via structures.

The disclosed technology relates to a power supply circuit that utilizes a double-sided printed circuit board (PCB) that has a first surface and a second surface. The second surface is disposed opposite the first surface. Mounted on the first surface is a first power stage and a first inductor. Mounted on the second surface is a second power stage and a second inductor. The second power stage is disposed opposite the first power stage. The second inductor is disposed opposite the first inductor.

A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.

A first insulating layer, a conductor layer included on a first main surface, an electronic component included on the first main surface and a second insulating layer stacked on the first insulating layer are included, a stacking direction of the first insulating layer and the second insulating layer is the same as a stacking direction of a first electrode layer, a second electrode layer, and the dielectric layer in the electronic component, and a height position of a main surface of the electronic component on an opposite side from a side of the first main surface is different from a height position of a main surface of the conductor layer adjacent to the electronic component on an opposite side from a side of the first main surface in the stacking direction.