Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.

Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.

The present invention relates to a multi-mode filter comprising a carrier on which is mounted a dielectric resonator having a covering of an electrically conductive material in which there is provided an aperture and a coupling structure for coupling input signals to the dielectric resonator or for extracting filtered output signals from the dielectric resonator. The carrier is provided with an enclosing formation of electrically conductive material, which enclosing formation is electrically coupled to the electrically conductive covering of the dielectric resonator, such that the covering and the enclosing formation together form an electrically conductive enclosure for the dielectric resonator. The enclosure formed from the covering of the dielectric resonator and the enclosing formation increases the isolation of the filter and reduces leakage. The filter of the present invention is particularly suitable for use in cascaded resonator filter arrangements, and in duplex/diplex filters.

Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; an electrical interface for a processor substrate at the first main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage. The power device module has at least one contact configured to receive the voltage provided at the second main side of the electrically insulating material. Distribution circuitry embedded in the electrically insulating material is configured to carry the lower voltage provided by the power device module to the first main side of the electrically insulating material.

An electronic component package structure and an electronic device are provided. The electronic component package structure includes at least: a substrate having a set attachment area for attaching an electronic component; a conductive lid having a top and a sidewall that extends toward the substrate, where one side of the sidewall close to the substrate has a bonding end, where the bonding end bonds the conductive lid to the substrate by using a non-conductive adhesive, and the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area; and the non-conductive adhesive is located between the substrate and the bonding end, and has a dielectric constant not less than 7 and a coating thickness not greater than 0.07 millimeters (mm). With the present invention, an Electromagnetic Interference (EMI) shielding effect of the shielding space can be improved.

A semiconductor integrated circuit device (101) includes a component built-in board (21) in which at least a first core layer (Co21) on which a first electronic component (C21) is mounted, a second core layer (Co22) on which a second electronic component (C22) is mounted, an adhesive layer (Ad21) arranged between the first core layer (Co21) and the second core layer (Co22), and wiring layers (L21-L28) are stacked; a third electronic component (SoC) mounted in a first core layer (Co21) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22) through the wiring layers (L21 to L28); and an external connection terminal (BE) formed in a second core layer (Co22) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22).

Methods and systems are provided for a power module. In one example, the power module may have a half-bridge configuration with electrical terminals arranged at opposite side of the power module, semiconductor chips arranged in a printed circuit board (PCB), a capacitor electrically coupled to the electrical terminals and arranged above and in contact with a top plate of the power module, and one or more connectors coupled to the PCB to couple the power module to external circuits. The power module may be directly cooled by flowing a coolant over the semiconductor chips.

A filtered connector is mounted on a casing and includes a connection port and a filter board. An electrode plate mounted on one end of the connection port and electrically isolated from the casing is securely mounted through a through hole of the casing. The filter board has a circuit board assembly, multiple grounding spring plates and multiple filtering capacitors. The circuit board assembly has a slot to be mounted through by the electrode plate. The grounding spring plates are mounted on a surface of the circuit board assembly and electrically contact the casing. The filtering capacitors are electrically connected between the electrode plate and the grounding spring plates. As the filter board is not mounted inside the connection port, only the filter board is to be mounted without replacing the connection port, thereby lowering users' expense in installation of the filter board.