Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect stub. In one instance, a printed circuit board (PCB) assembly may comprise a substrate and an interconnect (such as a via) formed in the substrate to route an electrical signal within the PCB. The interconnect may include a stub formed on the interconnect. At least a portion of the stub may be covered with an absorbing material to at least partially absorb a portion of the electric signal that is reflected by the stub. The absorbing material may be selected such that its dielectric loss tangent is greater than one, for a frequency range of a frequency of the reflected portion of the electric signal. A dielectric constant of the absorbing material may be inversely proportionate to the frequency of the reflected electric signal. Other embodiments may be described and/or claimed.

Optical stacks containing one or more patterned transparent conductor layers may be damaged by electrostatic discharges that occur during the optical stack manufacturing process. Such damage may result in non-conductive conductors within the patterned transparent conductor layer. An electrostatic discharge protected optical stack may include a substrate layer, a first anti-static layer having a sheet resistance of from about 10.sup.6 ohms per square (Ω/sq) to about 10.sup.9 Ω/sq, and a patterned transparent conductor layer. Methods of testing and assessing damage to patterned transparent conductors are provided.

A multilayer circuit board having a signal and power isolation circuit, which can suppress the capacitive coupling between a chip inductor and a ground layer below the chip inductor and also suppress the characteristic impedance change occurring in a mounting pad on a microstrip line. Portions of the inner-layer ground below both the mounting pad on the microstrip line and the chip inductors connected to the mounting pad are separately removed respectively as the signal transmission characteristic compensation removal portion, which is formed by removing a portion having a predetermined area and situated immediately below the mounting pad, and the inductor characteristic compensation removal portion, which is formed by removing a mounting-surface-below portion having a predetermined area and situated immediately below the chip inductors. The signal transmission characteristic compensation removal portion and the inductor characteristic compensation removal portion are electrically isolated from each other with the predetermined distance therebetween.

A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.

A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.

An electronic control device includes a conductive casing; a circuit board which is provided in the casing, and on which an electronic component including an integrated circuit is mounted; and a conductive conductor component that is provided on the circuit board, is disposed at a position higher than the electronic component, and has an elongated shape, in which a distance between the conductor component and the casing is shorter than a distance between the conductor component and the circuit board.

A device that includes a substrate including a plurality of metal layers, and a plurality of dielectric layers. The device further includes a first passive component including a first terminal, a second terminal, and a first body, mounted to the substrate on one of the plurality of metal layers. The first terminal is coupled to a first ground signal and the second terminal is coupled to a second ground signal such that the first passive component is shorted. The first passive component may be an inductor, a capacitor or a resistor. The first passive component is operable as a heat sink, a heat shield, an electromagnetic shield, or as a tuning inductor.

A wideband termination circuit layout is provided for high power applications. The circuit layout may include a dielectric layer having a first surface and a second surface. The circuit layout may also include an input port disposed over the first surface. The circuit layout may further include at least two resistive film patches disposed over the first surface of the dielectric layer and a tuning line between the at least two resistive films disposed over the first surface of the dielectric layer. The at least two resistive film patches are connected in series with the at least one tuning line.

A printed circuit board configured to be coupled to an automotive Ethernet connection includes a signal line layer on which a signal path is disposed, a ground layer disposed above the signal line layer, the ground layer including a digital ground and a chassis ground electrically insulated from the digital ground, a first capacitor and a second capacitor. The first capacitor and the second capacitor each couple the digital ground and the chassis ground. The first capacitor is positioned at a first distance from the signal path, and the second capacitor is symmetrically positioned, relative to the first capacitor, at a second distance from the signal path, where the second distance is substantially equal to the first distance.

An object of the present technique is to provide a transmission path that is capable of preventing deterioration of signal quality of a transmitted electric signal. The transmission path includes a reference portion, a first reflection suppressing portion, a second reflection suppressing portion, a first non-reference portion, and a second non-reference portion. The reference portion has an impedance that differs from each of the first non-reference portion and the second non-reference portion, and the first reflection suppressing portion has an impedance that is capable of suppressing a reflection coefficient of an impedance of the first transmission/reception terminal and an impedance of the first non-reference portion and has an electrical length that is equal to or shorter than an electrical length of the reference portion. The second reflection suppressing portion has an impedance that is capable of suppressing a reflection coefficient of an impedance of the second transmission/reception terminal and the impedance of the second non-reference portion and has an electrical length that is equal to or shorter than the electrical length of the reference portion.