H05K1/0251

SYSTEMS AND METHODS FOR BREAK OUT OF INTERCONNECTIONS FOR HIGH-DENSITY INTEGRATED CIRCUIT PACKAGES ON A MULTI-LAYER PRINTED CIRCUIT BOARD

A multi-layer printed circuit board having a first landing pad in a first layer and along a first axis arranged to receive a positive signal and a second landing pad in the first layer and along a second axis that is spaced away from the first axis longitudinally in the first layer and where the second landing pad arranged to receive a negative signal. A first buried in a second layer and along the first axis is spaced away from the first landing pad along the first axis. A second buried in the second layer and along the second axis is spaced away from the second landing pad along the second axis. A first signal connector provides a first electrical connection between the first landing pad and the second buried via and a second signal connector provides a second electrical connection between the second landing pad and the first buried via.

CIRCUIT BOARD HAVING COMPLEMENTARY SIGNAL CONDUCTING PATTERNS

A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.

PRINTED CIRCUIT BOARD AND WIRE ARRANGEMENT METHOD THEREOF

The present disclosure provides a printed circuit board and a wire arrangement method thereof. The printed circuit board includes a packaged chip and at least two connectors, wires of the packaged chip that are connected to different connectors are distributed on different board layers; and when the packaged chip is connected to one of the connectors, a via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out. The wires of the packaged chip that are connected to different connectors are distributed on different board layers. When the packaged chip is connected to one of the connectors, according to backdrilling of different depths, the via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out.

MATING BACKPLANE FOR HIGH SPEED, HIGH DENSITY ELECTRICAL CONNECTOR

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

Multilayer board
11659658 · 2023-05-23 · ·

A multilayer board includes a laminated insulating body, signal conductors inside the laminated insulating body and extending in a transmission direction, and ground conductors sandwiching each of the signal conductors in a lamination direction via the insulating base material layers. The multilayer board includes a parallel extending portion in which the signal conductors extend parallel and that includes signal conductors arranged separately from each other in a direction orthogonal to the transmission direction in a planar view in the lamination direction, and a signal conductor overlapping with the signal conductor in a planar view in the lamination direction and arranged separately from the signal conductor in the lamination direction. The parallel extending portion includes first and second regions arranged separately in a direction orthogonal to the transmission direction in a planar view in the lamination direction.

CIRCUIT BOARD STRUCTURE
20230156908 · 2023-05-18 · ·

A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.

HIGH-FREQUENCY CIRCUIT MODULE

A high frequency circuit module mounted on a first board that is a printed circuit board, includes: a second board; a high frequency circuit disposed on a first surface of the second board; a high frequency signal line disposed on the first surface of the second board, and extending from the high frequency circuit; and a matching member disposed on the first surface so as to cover at least a part of the high frequency signal line, and configured to adjust an impedance in the high frequency signal line. The matching member includes: a reference potential conductor separated from the high frequency signal line in a direction from a second surface, of the second board, opposite to the first surface, toward the first surface, the reference potential conductor being set at a reference potential; and a dielectric disposed between the reference potential conductor and the high frequency signal line.

TRACE ANYWHERE INTERCONNECT

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
20230209710 · 2023-06-29 · ·

Provided are a printed circuit board and a method for manufacturing the same, the printed circuit board including: an insulating member; a first pad disposed in the insulating member; a plurality of first vias respectively disposed on a lower side of the first pad in the insulating member and connected to the first pad; and a second via disposed on an upper side of the first pad in the insulating member and connected to the first pad.

PRINTED CIRCUIT BOARD HAVING A DIFFERENTIAL PAIR ROUTING TOPOLOGY WITH NEGATIVE PLANE ROUTING AND IMPEDANCE CORRECTION STRUCTURES
20230209726 · 2023-06-29 ·

A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.