Warpage reduction through laminate glass cloth design modification is described herein. In one example, a substrate for a microelectronic assembly, includes one or more glass-cloth containing layers. At least one of the glass-cloth containing layers includes a glass cloth having a weave including: a first plurality of parallel glass fibers, a second plurality of parallel glass fibers, and a third plurality of parallel glass fibers interwoven with one another in a plane. The second plurality of parallel glass fibers crosses the first plurality of glass fibers at a first angle, and the third plurality of parallel glass fibers crosses the first plurality of glass fibers at a second angle and crosses the second plurality of glass fibers at a third angle. In one example, the glass cloth weave includes a hexagonal pattern.

An aramid-based paper comprising at least 90 wt. % of aramid material, the aramid material including at least one of aramid shortcut and aramid fibrid, the paper including at most 40 wt. % aramid pulp, calculated on the total amount of aramid material, wherein the paper includes 0.1-10 wt. % of polyamido-amine epichlorohydrin (PAE). It has been found that the incorporation of 0.1-10 wt. % of polyamido-amine epichlorohydrin (PAE) into an aramid-based paper including at least 90 wt. % of aramid material calculated on the weight of the paper not including the PAE, the aramid material including at least one of aramid shortcut and aramid fibrid, the paper including at most 40 wt. % aramid pulp, leads to a surprising improvement of the z-strength and the tear strength of the paper.

A circuit board includes a substrate, a first magnetic structure, a first dielectric layer and an inductive coil. The substrate has a top surface and a bottom surface. The first magnetic structure is disposed on the top surface of the substrate. The first dielectric layer covers the substrate and the first magnetic structure. The inductive coil includes a first interconnect, a second interconnect and a plurality of conductive pillars. The first interconnect is disposed on the first dielectric layer. The second interconnect is disposed on the bottom surface of the substrate. The conductive pillars connect the first interconnect and the second interconnect. The first interconnect, the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.

An aspect of the present invention relates to a resin composition containing a polyphenylene ether compound having at least one of the groups represented by Formulas (1) and (2); and an allyl compound having a group represented by Formula (3).

The present disclosure relates to a dielectric composite may include a dielectric substrate overlying a reinforcement fabric layer. The dielectric substrate may include a resin matrix component, and a ceramic filler component. The ceramic filler component may include a first filler material. The particle size distribution of the first filler material may have a D.sub.10 of at least about 1.0 microns and not greater than about 1.7, a D.sub.50 of at least about 1.0 microns and not greater than about 3.5 microns, and a D.sub.90 of at least about 2.7 microns and not greater than about 6 microns.

Provided are a halogen-free phosphorus-free silicon resin composition, and prepreg and laminated board using the same, and printed circuit board, the silicon resin composition comprising the following components in parts by solid weight: 50-90 parts of an organic silicon resin, 20-80 parts of a vinyl-terminated silicon oil, 0.1-5 parts of a viscosity enhancing agent, 0-60 parts of a filler, 0.0001-0.5 parts of a catalyst, and 0.00001-0.1 parts of an inhibitor, a mole ratio between Si—H in a cross-linking agent and Si-Vi in the organic silicon resin being 1.0-1.7. The resin body of the resin composition is a thermosetting silicon resin, and the laminated board prepared thereby has good heat and flame resistance and an extremely low dielectric constant (Dk) and dielectric loss (Df).

A resin composition contains a component (A) being a polyphenylene ether in which the hydroxy group at an end of the main chain thereof has been modified with an ethylenically unsaturated compound, a component (B) being at least one of triallyl isocyanurate and triallyl cyanurate, and a component (C) being an organic peroxide containing no benzene ring. The component (C) is contained with a proportion of 0.1% to 7% by mass relative to 100% by mass of the total mass of the components (A), (B), and (C).

The present invention relates to an electrically conductive film characterized by being able to undergo elastic deformation, having little residual strain rate and exhibiting stress relaxation properties. More specifically, the present invention relates to an electrically conductive film wherein the stress relaxation rate (R) and the residual strain rate (alpha), as measured in a prescribed extension-restoration test, are as follows: 20%≦R≦95% and 0%≦α≦3%.

Provided is a glass cloth obtained by weaving a glass thread, which is made from a plurality of glass filaments, as a warp and weft. The average filament diameter of the glass filaments is 3.0-4.5 μm. The respective weaving densities of the warp and the weft constituting the glass cloth are, independently, 70-130 threads/25 mm. The standard deviation of weft width of the glass cloth is not more than 30 μm. The weft covering ratio R, which is represented by the expression R=Y/(25400/D) (where R is the weft covering ratio, Y is the average weft width, and D is the well weaving density) satisfies the relational expression 0.50≤R≤0.83.

A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.