Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.

A printed circuit board includes: a substrate structure having a first surface including a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having first to fourth edges and first to fourth corners formed by the first to fourth edges, and pad patterns on the second surface of the substrate structure, wherein the second surface includes a first region including a region corresponding to the chip mounting region and in contact with the first to fourth edges, respectively, and second regions adjacent to the first to fourth corners, respectively and spaced apart from each other by the first region, wherein the pad patterns include first pad patterns in the first region and surface-treated with a nickel/gold (Ni/Au) layer, and second pad patterns in the second regions and surface-treated with an organic solderability preservative.

The present disclosure relates to an electronic component, a voltage regulation module and a voltage stabilizer. The electronic component may include a substrate, a first electronic element and a second electronic element. The substrate may be provided with a first surface and a second surface that are opposite to each other. The first electronic element may be embedded in the substrate, and may be provided with a first electrical connection terminal and a second electrical connection terminal. The first electrical connection terminal may connect with a first surface of the substrate, the second electrical connection terminal may connect with a second surface of the substrate. The second electronic element may be arranged on the second surface of the substrate and electrically connected to the second electrical connection terminal. The second electronic element may form a stack with the substrate along the first direction.

A printed circuit board for mounting electrical components thereupon include: a first side; a second side opposite the first side; electrical connection points disposed on the surface of an exterior edge of the printed circuit board; and wherein the exterior edge of the printed circuit board is between the first side and the second side. Further a method of manufacturing a printed circuit board for mounting electrical components thereupon includes the steps of disposing interconnect structures within the printed circuit board adjacent to at least one edge of the printed circuit board; and removing material from the printed circuit board edge to expose the interconnect structures such that the exposed interconnect structures correspond to a component connection footprint.

In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.

The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.

A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.

A board-level pad pattern includes a printed circuit board (PCB) substrate; an exposed pad region disposed within a surface mount region of the base substrate; and multiple staggered ball pads disposed within the surface mount region arranged in a ring shape around the exposed pad region. The staggered ball pads includes first ball pads arranged in a first row and second ball pads arranged in a second row. The first ball pads in the first row are arranged at two different pitches, and the second ball pads in the second row are arranged at a constant pitch. Multiple square-shaped ball pads are arranged in a third row between the exposed pad region and the staggered ball pads.

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.