A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.

A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first buildup unit or at least one second buildup unit. The first buildup unit includes at least one first buildup body, the second buildup unit includes at least one second buildup body. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first and/or second buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.

Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.

A multilayer circuit board includes an upper surface and an opposing lower surface. An electrically insulating layer is disposed between the upper and lower surfaces. A plurality of electrically conductive upper and lower rear pads are disposed proximate a rear edge on the respective upper and lower surfaces for termination of a plurality of wires. The upper and lower rear pads include respective upper and lower rear ground pads substantially aligned with each other and configured for termination of ground wires. A plurality of electrically conductive front pads are disposed proximate a front edge for insertion into a connector and electrically connected to the upper and lower rear pads. An electrically conductive via extends from the upper rear ground pad to the lower rear ground pad and makes electrical and physical contact with each of the upper and lower rear ground pads.

A module includes: a substrate having a first surface; a first component mounted on the first surface; a resin film covering the first component along a shape of the first component and covering a part of the first surface; and one or more wires disposed to extend over the first component on a side of the resin film farther from the substrate.

A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of first and second surface-mount capacitors.

A hybrid coupler includes a 90° hybrid coupler and a first quarter wavelength conductive stub. The 90° hybrid coupler includes a coupling section, a first input transmission line that is coupled to the coupling section, a second input transmission line that is coupled to the coupling section, a first output transmission line that is coupled to the coupling section and a second output transmission line that is coupled to the coupling section. The first quarter wavelength conductive stub is coupled to the second output transmission line.

Disclosed are a circuit board and its preparation method. The circuit board includes a base layer, a transmission wire layer including multiple conductor tabs, and an insulating and thermally conductive layer including multiple thermally conductive portions. A gap is defined between each adjacent two of the multiple conductor tabs to expose at least a portion of the base layer, and the gap is filled with a corresponding thermally conductive portion. A height of the thermally conductive portion is larger than heights of each adjacent two of the multiple conductor tabs to define a connection groove. The circuit board the disclosure providing enhances heat dissipation performance of circuit boards.

A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.