An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids disposed at a top surface and a bottom surface of the PCB, respectively. Each grid includes a plurality of footprint pins, and a plurality of vias extending through the PCB to the top and bottom surfaces. Each footprint pin includes a connecting end and a free end that opposes the connecting end. Each via includes a contact end located at one of grids and is in electrical contact with the connecting end of one of the footprint pins, and each via further includes a non-contact end that is located at the other of the grids and is not in electrical contact with any of the footprint pins. First and second connectors are mounted to the PCB top and bottom surfaces and connect with the footprint pins of the first and second grids.

A multilayer circuit board and a manufacturing method thereof are provided. The multilayer circuit board includes: a first board having a first conductive via hole; a first conductive layer formed on the first board and the first conductive via hole; a second board disposed on the first board and the first conductive layer and having a second conductive via hole; and a second conductive layer formed on the second board and the second conductive via hole. The first conductive layer and the second conductive layer contact with each other and cooperatively define a connecting part, and the connecting part of the first conductive layer and the second conductive layer includes concave-convex surfaces for engaging with each other.

A multilayer circuit board and a manufacturing method thereof are provided. The multilayer circuit board includes: a first board having a first conductive via hole; a first conductive layer formed on the first board and the first conductive via hole; a second board disposed on the first board and the first conductive layer and having a second conductive via hole; and a second conductive layer formed on the second board and the second conductive via hole. The first conductive layer and the second conductive layer contact with each other and cooperatively define a connecting part, and the connecting part of the first conductive layer and the second conductive layer includes concave-convex surfaces for engaging with each other.

In an embodiment, an inductor comprises a first trace, where the first trace has a first end and a second end, and where the first trace extends along a first plane, and a first conductive path over the first end of the first trace, where the first conductive path extends along a second plane that is substantially orthogonal to the first plane. In an embodiment, the inductor further comprises a second conductive path over the second end of the first trace, where the second conductive path extends along a third plane that is substantially parallel to the second plane, and a second trace over the first conductive path, where the second trace extends along a fourth plane that substantially parallel to the first plane. In an embodiment, the inductor further comprises a third trace over the second conductive path, where the third trace extends along the fourth plane.

An electronic device includes a circuit board, and first and second elements. The first element includes a first connection portion including a recess portion, and first connection portion side electrodes exposed to the first connection portion. The second element includes a second connection portion and second connection portion side electrodes exposed to the second connection portion. The circuit board includes first and second board side electrodes respectively disposed at positions opposed to each other in plan view. The first connection portion side electrode and the second connection portion side electrode are joined to the first board side electrode and the second connection portion side electrode connected to each other. The first connection portion side electrode and the first board side electrode are disposed along the recess portion in plan view of the circuit board.

In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

A motherboard includes a multilayer printed circuit board (PCB), a central processing unit (CPU) slot, at least one first memory slot, at least one second memory slot, a plurality of first traces, and a plurality of second traces. The CPU slot, the first memory slot, and the second memory slot are disposed on the first wiring layer of the multilayer PCB, and the second memory slot is disposed between the first memory slot and the CPU slot. The first traces are disposed on the first wiring layer of the multilayer PCB. The CPU slot is electrically connected to the first memory slot by the first traces. The second traces are disposed on the second wiring layer of the multilayer PCB which is different from the first wiring layer, and the CPU slot is electrically connected with the second memory slot by the second traces.

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

A printed wiring board includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings each include a first via conductor disposed outside a first region, a second region, and a third region in a plan view, and a first conductor pattern extending from the first via conductor to the first region. The plurality of second wirings each include a second via conductor disposed outside the first region, the second region, and the third region, and a second conductor pattern extending from the second via conductor to the first region. A fourth region overlaps with a fifth region in the plan view, the fourth region being a region in which a plurality of first conductor patterns are disposed, the fifth region being a region in which a plurality of second conductor patterns are disposed.