A fingerprint sensor packaging module includes a light-pervious cover layer, a conductive pattern layer on the light-pervious cover layer, a finger sensing chip on the conductive pattern layer, a circuit board on the light-pervious cover layer, and a package member. The conductive pattern layer includes a plurality of pads. The fingerprint sensing chip is electrically connected to the conductive pattern layer by contacting to the pads. The circuit board is electrically connected to the conductive pattern layer and has a hole and the hole exposes the fingerprint sensing chip. The fingerprint sensing chip is disposed in the hole. The package member disposed in the hole and at least cover the fingerprint sensing chip.

A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.

A method for manufacturing a circuit-board structure wherein a conductor foil is provided on an insulating material layer, a resist layer is spread on the conductor foil and a recess formed in the conductor foil and insulating material layer. The resist layer is patterned to form a conductor-pattern having openings wherein conductor patterns may be grown. A component is attached to the conductor foil and conductor pattern and conductor material is removed which does not form part of a conductor pattern.

A fingerprint sensor packaging module includes a light-pervious cover layer, a conductive pattern layer on the light-pervious cover layer, a finger sensing chip on the conductive pattern layer, a circuit board on the light-pervious cover layer, and a package member. The conductive pattern layer includes a plurality of pads. The fingerprint sensing chip is electrically connected to the conductive pattern layer by contacting to the pads. The circuit board is electrically connected to the conductive pattern layer and has a hole and the hole exposes the fingerprint sensing chip. The fingerprint sensing chip is disposed in the hole. The package member disposed in the hole and at least cover the fingerprint sensing chip.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

A wiring substrate includes an insulation layer, separated wires formed on a first surface of the insulation layer, a first plating layer formed on a first surface of each of the wires, a reflection layer including a first opening that exposes at least a portion of the first plating layer as a connection pad, and an electronic component mounted on a second surface of each of the wires, which is located on an opposite side of the first surface of each of the wires. The electronic component is embedded in the insulation layer.

A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure, and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure. The second interconnect layer has an interconnect density higher than those of the first and the third interconnect layers. The first insulating layer has a through hole penetrating the first insulating layer, and an electronic component electrically connected to the second interconnect layer is disposed inside the through hole. An embedding resin covering the electronic component is provided inside the through hole, and extends to cover the first insulating layer and fills in between the first and second insulating layers.

An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; a heat dissipation structure disposed around the antenna on the upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of each of the antenna and the heat dissipation structure.

An element embedded printed circuit board includes: a substrate including an insulation layer, a first circuit layer formed on a first surface of the insulation layer, and a second circuit layer formed on a second surface of the insulation layer; and an element including an electrode part and embedded in the insulation layer, wherein the electrode part is in contact with the first circuit layer.

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.