Methods, systems, and apparatus for fabricating a circuit board. The method includes fabricating, using an additive manufacturing device, a trace layer, a sacrificial layer, a rail layer and a lid. The method includes placing the sacrificial layer on the trace layer such that the raised traces protrude through corresponding openings of the sacrificial layer. The method includes depositing a conductive material on top of the sacrificial layer and the plurality of traces. The method includes removing the sacrificial layer from the trace layer and placing the rail layer on the trace layer such that the raised traces align with the corresponding openings of the rail layer. The method includes connecting one or more electrical components and melting a sealing sheet on top of the rail layer and the electrical components to reinforce connections and to provide protection. The method includes placing the lid on top of the sealing sheet.

Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

The present invention provides a method for forming trace of circuit board, applicable to enhance the yield rate of circuit board and including the following step:(a) providing a plastic substrate; (b) forming an ink layer on a surface of the plastic substrate, the ink layer comprises at least one hollow pattern; (c) forming a copper plating layer in the at least one hollow pattern; and (d) removing the ink layer.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A substrate has an insulating layer 11; an adhesion layer 200 provided on the insulating layer 11; and a metal layer 220 provided on the adhesion layer 200. The adhesion layer 200 has an adhesion main body layer 210 and an anchor body 215 protruded from a front surface of the adhesion main body layer 210 or has a redox layer 250.

A component carrier including an electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end. The electronic component directly contacts the component contacting end. The wiring contacting end is directly electrically contacted to the wiring structure. The exterior surface portion of the coupling structure has homogeneous ablation properties and surface recesses filled with an electrically conductive wiring structure. A method includes embedding an electronic component in an electrically insulating core, providing a coupling structure with a conductive connection having a component end and a wiring end, connecting the electronic component directly to the component end, providing a surface portion of the coupling structure with homogeneous ablation properties, patterning the surface portion with recesses and filling the recesses with a wiring structure such that the wiring end is contacted directly.

Provided is a method of manufacturing a printed circuit nano-fiber web. A method of manufacturing a printed circuit nano-fiber web according to an embodiment of the present invention includes (1) a step of electrospinning a spinning solution including a fiber-forming ingredient to manufacture a nano-fiber web; and (2) a step of forming a circuit pattern to coat an outer surface of nano-fiber included in a predetermined region on the nano-fiber web using an electroless plating method. According to the present invention, a circuit pattern-printed nano-fiber web having flexibility and resilience suitable for future smart devices may be realized. In addition, a circuit pattern may be densely formed to a uniform thickness on a flexible nano-fiber web using an electroless plating method, and the flexible nano-fiber web may include a plurality of pores. Accordingly, since the printed circuit nano-fiber web may satisfy waterproofness and air permeability characteristics, it can be used in various future industrial fields including medical devices, such as biopatches, and an electronic device, such as smart devices.