The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A printed wiring board includes a laminate including resin insulating layers and conductor layers such that the resin insulating layers and the conductor layers are laminated alternately and that the laminate has a through hole opening to a first surface of the laminate and a component accommodating cavity that accommodates an electronic component and having an opening part formed on a second surface of the laminate on the opposite side with respect to the first surface. The through hole is formed through the laminate such that the through hole is extending to the component accommodating cavity, and the laminate has a resin coating formed on an inner wall surface of the through hole.

Implementations described and claimed herein provide thin film devices and methods of manufacturing and implanting the same. In one implementation, a shaped insulator is formed having an inner surface, an outer surface, and a profile shaped according to a selected dielectric use. A layer of conductive traces is fabricated on the inner surface of the shaped insulator using biocompatible metallization. An insulating layer is applied over the layer of conductive traces. An electrode array and a connection array are fabricated on the outer surface of the shaped insulator and/or the insulating layer, and the electrode array and the connection array are in electrical communication with the layer of conductive traces to form a flexible circuit. The implantable thin film device is formed from the flexible circuit according to the selected dialectic use.

An integrated circuit substrate, and method of production, includes an internal patterned mask layer defined by multiple mask units that are spaced apart by gaps on a partially or completely removable carrier, and an internal conductive trace layer formed by one or more internal conductive traces that are deposited into the gaps of each internal patterned mask layer such that each gap is occupied with an internal conductive trace. The internal patterned mask layer is made of a photoimageable dielectric material that is retained in the integrated circuit substrate. Other embodiments include the formation of permanent or removable external patterned mask layer and external conductive trace layer on the topmost and optionally the bottommost internal patterned mask layer and internal conductive trace layer. The substrate can also include an insulating layer to partially or completely encapsulate the external conductive trace layer upon removal of the external patterned mask layer.

A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

An object of the present invention is to provide a film having a plated-layer precursor layer which is capable of forming a metal layer having excellent roll-to-roll productivity and excellent adhesiveness to a substrate. Another object of the present invention is to provide a film having a patterned plated layer as well as an electroconductive film and a touch panel using the same.

The film having a plated-layer precursor layer of the present invention is a film having a plated-layer precursor layer including a substrate, and an undercoat and a plated-layer precursor layer disposed on the substrate in this order from the substrate side, in which the undercoat has a hardness on the surface thereof of 10 N/mm.sup.2 or less and a friction coefficient with release paper of 5 or less.

The present invention refers to a method of preparing a high density interconnect printed circuit board (HDI PCB) including microvias filled with copper comprising the steps of: a1) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a cover layer, and (iii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b1) depositing a conductive layer; or a2) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b2) depositing a conductive layer; and c) electrodepositing a copper filling in the microvia and a first copper layer on the conductive layer which form together a planar surface and the thickness of the first copper layer is from 0.1 to 3 ?m.

A novel method for the manufacturing of fine line circuitry on a transparent substrates is provided, the method comprises the following steps in the given order providing a transparent substrate, depositing a pattern of light-shielding activation layer on at least a portion of the front side of said substrate, placing a photosensitive composition on the front side of the substrate and on the pattern of light-shielding activation layer, photo-curing the photosensitive composition from the back side of the substrate with a source of electromagnetic radiation, removing any uncured remnants of the photosensitive composition; and thereby exposing recessed structures and deposition of at least one metal into the thus formed recessed structures whereby a transparent substrate with fine line circuitry thereon is formed. The method allows for very uniform and fine line circuitry with a line and space dimension of 0.5 to 10 m.