A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.

A composite circuit board includes an insulation layer, an inner circuit layer, a first conductive layer and a second conductive layer embedded in the insulation layer, a third conductive layer and a fourth conductive layer formed on opposite surfaces of the insulation layer. The third conductive layer electrically connects with the first conductive layer. The fourth conductive layer electrically connects with the second conductive layer. The inner circuit layer is in a middle portion of the insulation layer. The first conductive layer and the second conductive layer respectively forms on opposite sides of the inner circuit layer. The insulation layer forms a plurality of first through holes between the first conductive layer and the inner circuit layer, a plurality of second through holes between the second conductive layer and the inner circuit layer.

An electroless plating method for a low temperature co-fired glass ceramic substrate includes: a degreasing and activation treatment step of degreasing and activating a surface of a wiring pattern formed of a silver sintered body; a catalyzing step of providing a catalyst onto the surface of the wiring pattern formed of a silver sintered body; and an electroless multi-layered coating plating treatment step of forming a multi-layered electroless plating coating on the surface of the wiring pattern formed of a silver sintered body. The method further includes, between the degreasing and activation treatment step and the catalyzing step, a silver precipitation treatment step of precipitating silver on a glass component present on the surface of the wiring pattern formed of a silver sintered body after the degreasing and activation treatment step, and the catalyzing step includes providing the catalyst also to the silver precipitated in the silver precipitation treatment step.

An assembly is provided that includes a semiconductor device positioned on a frame and connected to electroplated traces via wire bonding. A connector can be integrated into the frame. Terminals can be molded into the frame. Traces can be connected to the terminals so as to provide a three-dimensional circuit.

Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.

The present disclosure relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.

A wiring substrate at which a metal wire is formed includes a substrate containing a resin as a main component and an organic substance having a hydroxyl group; and a metal plating layer constituting the metal wire. A formation portion of the metal wire at one surface of the substrate is rougher than a non-formation portion of the metal wire at the one surface of the substrate, and has the organic substance in a state of being embedded in the resin, and a catalyst. The wiring substrate with such a configuration can increase the adhesion of the metal wire to the substrate.

A process of forming an article utilizes an ultra-thin, removable, catalytic film for Laser Direct Structuring (LDS). The process includes forming a film from a laser-activatable material, the film exhibiting thickness of less than 100 m; applying the film to a black or opaque substrate to form a film-substrate element; applying a laser to the film-substrate element; removing a portion of the film from the film-substrate element; and applying metal plating to a portion of the black or opaque substrate. Removal of the film from the film-substrate element may follow metal plating of the black or opaque substrate. An article formed by the process may be useful in a computer device, electromagnetic interference device, printed circuit, Wi-Fi device, Bluetooth device, GPS device, cellular antenna device, smart phone device, automotive device, medical device, sensor device, RF antenna device, LED device, RFID device, or a component of a cell phone antenna.

A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.