A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 ?m, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

A wiring substrate includes a surface layer having electrical insulation properties and a connection terminal having electrical conduction properties and protruding from the surface layer. The connection terminal includes a base portion, a covering portion and a filling portion. The base portion of the connection terminal is made of an electrically conductive first metal and located adjacent to the surface layer so as to extend through the surface layer and protrude from the surface layer. The covering portion of the connection terminal is made of an electrically conductive second metal having a melting point lower than that of the first metal and located so as to cover the base portion. The filling portion of the connection terminal is made of at least one of the second metal and an alloy containing the first and second metals and located so as to fill a hollow in the base portion.

To provide a surface-treated copper foil that is capable of favorably decreasing the transmission loss even used in a high frequency circuit board and has an improved peel strength on adhering to an insulating substrate, such as a resin. A surface-treated copper foil containing a copper foil, and a surface treatment layer containing a roughening treatment layer on at least one surface of the copper foil, wherein on observation of the copper foil from the side of the surface having the roughening treatment layer, the roughening treatment layer has an average length of roughening particles of 0.030 m or more and 0.8 m or less, the roughening treatment layer has an average number of gap portions between the adjacent roughening particles of 20/100 m or more and 1,700/100 m or less, and the roughening treatment layer has a total frequency of an overlap frequency and a contact frequency of roughening particles of 120/100 m or less.

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 m, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

A wiring substrate includes a wiring layer, an insulating layer covering the wiring layer, and a protruding electrode including a protruding metal layer and a surface metal layer. The protruding metal layer is connected to the wiring layer in an opening of the insulating layer, extends from within the opening to be stepped at the edge of the opening to extend outward onto the insulating layer, and includes a first surface contacting a surface of the insulating layer around the opening, a second surface, and a peripheral surface extending between the first and second surfaces, and bent inward to form a space between the peripheral surface and the surface of the insulating layer. The surface metal layer covers the protruding metal layer without contacting the surface of the insulating layer, and is formed of a metal having a lower melting point than the protruding metal layer.

A printed circuit board according the present embodiment includes an insulating layer; at least one circuit pattern or pad formed on the insulating layer; a solder resist having an opening section exposing the upper surface of the pad and formed on the insulating layer and a bump formed on the pad exposed through the opening section of the solder resist and having a lower area narrower than the upper area.

An electronic device is provided that includes a vertical chassis wall having an aperture; a horizontal circuit board that extends toward the vertical chassis wall; an F-connector connected to the horizontal circuit board on a first side and extending out of the vertical chassis wall through the aperture; and an inner shield that shields a radiofrequency circuit components mounted on the first side of the circuit board. The inner shield includes tabs that extend partially into solder plated clearance holes in the horizontal circuit board and are reflow-soldered into the clearance holes. The tabs have distal ends that terminate between a plane of the first side and a plane of a second side of the circuit board.

A tin-based solder melt or aqueous tin plating bath composition comprising a source of tin and a stabilizing additive of chemical structure: ##STR00001##
wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7, R.sup.8, R.sup.9, and R.sup.10 are independently selected from hydrogen atom, hydrocarbon groups R having at least one and up to twelve carbon atoms, groups OR wherein R is selected from hydrogen atom and hydrocarbon groups R, and halogen atoms, and wherein any two, three, or four of R.sup.1, R.sup.2, R.sup.3, R.sup.4, and R.sup.5 or any two, three, or four of R.sup.6, R.sup.7, R.sup.8, R.sup.9, and R.sup.10 are optionally interconnected to form a fused ring system; R.sup.11 and R.sup.12 are independently selected from hydrogen atom and hydrocarbon groups R; and r is either 0 or 1. Methods for coating and/or bonding metal substrates by use of the above-described solder compositions are also described.

A method for manufacturing a printed wiring board includes forming a removable layer over first pads in central portion of an interlayer insulation layer to mount IC chip, forming on the interlayer and removable layers a resin insulation layer having openings exposing second pads in peripheral portion of the interlayer layer to connect second substrate, forming a seed layer on the resin layer, in the openings and on the second pads, forming on the seed layer a plating resist having resist openings exposing the openings of the resin layer with diameters greater than the openings, filling the resist openings with electrolytic plating such that metal posts are formed in the resist openings, removing the resist, removing the seed layer exposed on the resin layer, and removing the removable layer and the resin layer on the removable layer such that cavity exposing the first pads is formed in the resin layer.