Please move the Abstract from the first page of the published international application (International Publication No. WO 2017/011703) to the end of the present application, immediately following the claims.

A polymer film is applied onto a surface of a laminated printed circuit board subassembly having vias. Holes are created in the polymer film to access the vias while the polymer film remains covering adjacent areas. The polymer film with holes allows placement of hole-fill paste in the vias while preventing unwanted hole-fill paste placement or migration to adjacent areas. After filling the vias with hole-fill paste, the hole-fill paste is preferably at least partially hardened or cured, and the polymer film is preferably removed, facilitating further assembly of a printed circuit board without unwanted hole-fill paste in other areas which could be difficult to remove, The invention includes improved processes for fabricating printed circuit boards, and is particularly useful for irregular circuit boards and rigid flex circuit boards. The invention also includes covered laminated printed circuit board subassemblies, covered with a removable polymer film.

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

An apparatus includes a printed circuit board (PCB), a solder pad, a signal via, a plurality of metalized vias, and a waveguide. The PCB has a first surface opposite a second surface and includes a first metal layer, a second metal layer having a waveguide opening, and a PCB channel region from the waveguide opening in the second metal layer to the second surface. The solder pad is positioned on the first surface of the PCB over the channel region, and the signal via is coupled to the solder pad and a via pad in the second metal layer within the waveguide opening. The plurality of metalized vias extend from the first surface to the second surface of the PCB and form a boundary around the channel region. The waveguide is affixed to the waveguide opening in the second metal layer.

A method for manufacturing such multilayer printed circuit board includes providing a metal laminated structure including a first type metal layer and a second type metal layer, pressing a patterned dry film layer and a protective film layer on two surfaces of the metal laminated structure, the dry film layer exposing the second type metal layer; etching the second type metal layer to form a first conductive circuit layer; etching a first type metal layer to form a second conductive circuit layer, the first conductive circuit layer and the second conductive circuit layer defining an inner circuit laminated structure; removing the dry film layer; and forming a first adding-layer circuit base board and a second adding-layer circuit base board on two surfaces of the inner laminated structure.

A printed wiring board includes a first insulating layer, a second conductor layer including first and second circuits, a second insulating layer covering the second conductor layer on the first insulating layer, a third conductor layer including first and second circuits, a third insulating layer covering the third conductor layer on the second insulating layer, a fourth conductor layer including first circuit, a second via conductor connecting the first circuits in the second and third conductor layers through the second insulating layer, and a first skip via conductor penetrating through the second circuit in the third conductor layer and connecting the second circuit in the second conductor layer and the first circuit in the fourth conductor layer through the second and third insulating layers. The second and third conductor layers are formed such that the second conductor layer has thickness t2 larger than thickness t3 of the third conductor layer.

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

A method for embedding a discrete electrical device in a printed circuit board (PCB) is provided, which includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to a conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first device contact and the conductive structure in the first layer; and establishing a second electrical connection between a second device contact and a second layer, the second layer being one of the conductive layers of a second horizontal core section.

A line card of a set of line cards is configured to be coupled to a set of switch-fabric cards to collectively define at least a portion of an orthogonal cross fabric without a midplane board. The line card has an edge portion, a first side and a second side, opposite the first side. The line card includes a set of first set of connectors and a second set of connectors. The first set of connectors is disposed along the edge portion on the first side of the line card and the second set of connectors is disposed along the edge portion on the second side of the line card.

A power supply unit of an aerosol generating device, the power supply unit includes: a power supply; a first switch configured to adjust electric power to be supplied from the power supply to an atomizer that atomizes an aerosol source; and a circuit substrate on which the first switch is mounted. The circuit substrate includes: a first layer that is a front layer on which the first switch is mounted, a second layer that is different from the first layer, a first via that penetrates the first layer and is connected to the first switch, a second via that penetrates the first layer or the second layer and is spaced apart from the first via, and a first conductive pattern that is provided on the second layer and connects the first via and the second via.