A component-embedded substrate includes first to sixth thermoplastic resin bases, a first electronic component in the second thermoplastic resin base and including a first terminal, and a second electronic component in the fifth thermoplastic resin base and including a second terminal. The first terminal faces the second electronic component in a stacking direction. The second terminal faces the first electronic component in the stacking direction. A first planar conductor to which the first terminal is directly bonded is provided on the third thermoplastic resin base. An interlayer connection conductor to which the second terminal is directly bonded and in communication with the first planar conductor is provided in or on the fourth thermoplastic resin base.

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

In a method for manufacturing a multilayer substrate, first, a via hole is formed in a first insulating layer and a second insulating layer and filled with conductive paste. Subsequently, the first insulating layer and the second insulating layer are stacked on each other. Next, the conductive paste is cured to form a via conductor while the first insulating layer and the second insulating layer are integrated through thermal pressing. Then, a penetrating hole that penetrates the via conductor in the laminating direction is formed.

A circuit board according to an embodiment comprises a first insulating layer; a first pattern layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and including a cavity; and a barrier layer disposed on a first pattern layer vertically overlapping with the cavity among the first pattern layers, wherein the upper surface of the first insulating layer includes: a first upper surface vertically overlapping a lower surface of the cavity, and a second upper surface that does not vertically overlap the lower surface of the cavity, wherein the first pattern layer includes: a first pattern part disposed on the first upper surface of the first insulating layer, and a second pattern part disposed on the second upper surface of the first insulating layer, wherein an upper surface of the first pattern part is exposed through the cavity without contacting the first and second insulating layers, and wherein the barrier layer is disposed on the upper surface of the first pattern part.

A printed circuit board includes a first substrate including a first antenna pattern; a second substrate disposed on a first substrate and including a second antenna pattern; a metal layer disposed between the first and second substrates; and a bonding layer disposed between the first and second substrates. At least one of the first and second substrates has a cavity having at least a portion disposed between the first and second antenna patterns, each of the first and second substrates includes an organic material, and the bonding layer includes an inorganic material.

The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

A method of manufacturing a component carrier, wherein the method comprises stamping a surface profile in a design layer, forming a metallic base structure in at least one indentation of the profiled design layer at least partially by electroplating, and electroplating an electroplating structure in the at least one indentation on or above the metallic base structure.