The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a base; forming a functional stack on the base, wherein the functional stack includes a first doped layer, a second doped layer and a third doped layer that are stacked sequentially, the first doped layer is provided on the base, dopant ions in the second doped layer are different from dopant ions in the first doped layer, and the dopant ions in the first doped layer are the same as dopant ions in the third doped layer; and removing a part of the functional stack to form a plurality of active pillars arranged at intervals.

Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.

Disclosed herein is a method that includes epitaxially growing SiGe layer on a silicon substrate, etching the SiGe layer and the silicon substrate to form an active region covered with the SiGe layer, first etching the SiGe layer formed on a first region of the active region without etching the SiGe layer formed on a second region of the active region to form a first trench, and second etching the SiGe layer remaining on an inner wall of the first trench.

Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

A semiconductor device includes a bit line structure and a storage contact spaced apart from each other over a substrate; a bit line spacer formed on a sidewall of the bit line structure; a landing pad formed over the storage contact; a boron-containing capping layer disposed between the bit line structure and the landing pad; a boron-containing etch stop layer over the boron-containing capping layer; and a capacitor including a storage node coupled to the landing pad by passing through the boron-containing etch stop layer.

The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.

A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

An IC package includes a substrate, a first monolithic die, a second monolithic die and a third monolithic die. A processing unit circuit is formed in the first monolithic die. A plurality of SRAM arrays are formed in the second monolithic die, wherein the plurality of SRAM arrays include at least 5-20 G Bytes. A plurality of DRAM arrays are formed in the third monolithic die, wherein the plurality of DRAM arrays include at least 64-512 G Bytes. The first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate. The third monolithic die is electrically connected to the first monolithic die through the second monolithic die.