A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.

A semiconductor structure includes: a substrate; bit lines located in the substrate and including a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward the top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and transistors located on a top surface of the contact portion, the extension direction of a channel of the transistor being perpendicular to a plane where the substrate is located.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.

A semiconductor structure and a method for manufacturing a semiconductor structure are provided, which relate to the technical field of semiconductors. The semiconductor structure includes a substrate and a plurality of first conductive layers. The substrate includes a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction. A plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches. The first direction intersects with the second direction. Each of the plurality of first conductive layers is arranged on each of sidewalls, which are arrayed in the first direction, of a respective one of the plurality of active pillars.

A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.

A method for fabricating a semiconductor device includes providing a substrate; forming a bit line conductive layer on the substrate and a bit line inner capping layer on the bit line conductive layer to form a bit line structure; a bit line structure; forming a bit line spacer capping layer covering the bit line structure; forming a cell contact adjacent to the bit line structure; forming a blanket pad layer on the bit line spacer capping layer and the cell contact; forming a plurality of pad openings along the blanket pad layer and extending to the bit line spacer capping layer and the bit line inner capping layer to turn the blanket pad layer into a plurality of landing pads; and selectively forming a sealing layer to form a plurality of air gaps between the bit line conductive layer and the plurality of landing pads.

The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

An embodiment provides a method for fabricating a semiconductor structure. The method includes: providing a semiconductor substrate having an active area, the active area including a first active area and a second active area isolated from each other; forming a bitline contact groove on the semiconductor substrate, the bitline contact groove exposing the first active area; forming an etch stop layer covering a sidewall of the bitline contact groove, the etch stop layer exposing a partial area of the first active area at a bottom of the bitline contact groove; etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove, the pit being at least partially positioned in the first active area; removing the etch stop layer; forming a bitline structure; and forming a conductive plug electrically connected to the second active area.

A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.