Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Three-dimensional (3D) semiconductor devices and fabricating methods are disclosed. The semiconductor device includes an array of vertical transistors. Each vertical transistor includes a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body. Each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the all-around gate structures of the row of the vertical transistors. Adjacent rows of the vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction. The array of vertical transistors are aligned along a third lateral direction different from the first lateral direction and the second lateral direction.

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F.sup.2 3D cross-point memory array has been formed.

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F.sup.2 3D cross-point memory array has been formed.

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4 F.sup.2 3D cross-point memory array has been formed.