This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface.

A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

A semiconductor device includes a buried word line in a substrate and extending along a first direction, a stacked nanowire structure over the buried word line, a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively. A method for manufacturing the semiconductor device includes the steps of forming a buried word line extending along a first direction in a substrate, mounting an epitaxy silicon sheet on the substrate and the buried word line, forming a stacked nanowire structure over the buried word line, forming a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and forming a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively.

A semiconductor device includes a buried word line in a substrate and extending along a first direction, a stacked nanowire structure over the buried word line, a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively. A method for manufacturing the semiconductor device includes the steps of forming a buried word line extending along a first direction in a substrate, mounting an epitaxy silicon sheet on the substrate and the buried word line, forming a stacked nanowire structure over the buried word line, forming a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and forming a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively.

Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.