A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.

Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate and bit line structures on the substrate; forming a first isolation layer, the first isolation layer being located on side walls of the bit line structures and on the substrate; forming a second isolation layer, the second isolation layer covering the first isolation layer located on the side walls of the bit line structures, and exposing the first isolation layer located on the substrate; removing the first isolation layer exposed by the second isolation layer and part of the first isolation layer below the second isolation layer, so that remaining of the first isolation layer is recessed compared to the second isolation layer toward the side walls of the bit line structures to form a groove.

A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is over and electrically connected to a second portion of the bottom electrode. The spacer is adjacent at least a sidewall of the second portion of the bottom electrode.

Provided are a capacitor, an electronic device including the same, and a method of manufacturing the same, the capacitor including a first thin-film electrode layer; a second thin-film electrode layer; a dielectric layer between the first thin-film electrode layer and the second thin-film electrode layer; and an interlayer between the dielectric and at least one of the first thin-film electrode layer or the second thin-film electrode layer, the interlayer including a same crystal structure type as and a different composition from at least one of the first thin film electrode layer, the second thin film electrode layer, or the dielectric layer, the interlayer including at least one of a anionized layer or a neutral layer.

A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed.

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing an initial structure, where the initial structure includes a capacitive contact region and a target layer located on the capacitive contact region; forming a first bottom electrode structure in the target layer, where the first bottom electrode structure is connected to at least part of the capacitive contact region; and forming, in the target layer, a second bottom electrode structure connected to the first bottom electrode structure.