The embodiments of the present application relate to the field of semiconductor technologies, and disclose a semiconductor structure manufacturing method. The method includes: forming a hard mask on a semiconductor substrate; forming a photoresist film on the hard mask; patterning the photoresist film to form a patterned photoresist layer having first openings and second openings, wherein the second openings are disposed at intervals between the first openings; etching the hard mask by taking the patterned photoresist layer as a mask to form a patterned hard mask layer having a plurality of third openings, wherein the third openings correspond to the first openings and the second openings; and etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form holes along the third openings. According to this method, the manufacturing efficiency and the quality of the holes are improved simultaneously.

The present disclosure provides a method of manufacturing a semiconductor device, The method includes providing a substrate, forming a metallization layer on the substrate, forming an upper dielectric layer over the metallization layer, forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer penetrating the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first axis, and the second sacrificial layer is free from overlapping the first sacrificial layer and the third sacrificial layer along the first axis, forming a width controlling structure between the first sacrificial layer and the third sacrificial layer, wherein the width controlling structure defines a recess exposing the upper dielectric layer, forming a protective layer within the recess, removing the width controlling structure to expose a portion of the metallization layer.

An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed.

A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

A semiconductor device includes a substrate. The semiconductor device further includes a first transistor on the substrate, wherein the first transistor includes a first source/drain electrode in the substrate. The semiconductor device further includes a second transistor on the substrate, wherein the second transistor includes a second source/drain electrode. The semiconductor device further includes an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate, and a sidewall of the insulating layer above the substrate is aligned with a sidewall of the insulating layer within the substrate.

A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

An embedded dynamic random-access memory cell includes a wordline to supply a gate signal, a selector thin-film transistor (TFT) above the wordline and that includes an active layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the active layer in response to the gate signal, a bitline to transfer the memory state and coupled to and above the first region of the active layer, a storage node coupled to and above the second region of the active layer, and a metal-insulator-metal capacitor coupled to and above the storage node and configured to store the memory state. In an embodiment, the wordline is formed in a back end of line process for interconnecting logic devices formed in a front end of line process below the wordline, and the selector TFT is formed in a thin-film process.

Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing a bulk substrate with a first doped layer thereon, depositing a first hard mask over the substrate, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, where the grown second polysilicon material and epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material.