The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.

Electrical device comprising a field effect transistor (FET). The FET includes a substrate with a channel region thereon, the channel region including a film of single-walled carbon nanotubes located on the substrate, metallic source and drain electrodes layers on the channel region and gate structure covering a portion of channel region and located between the metallic source and drain electrode layers. The gate structure includes a gate dielectric layer on the portion of the channel region and a gate electrode layer on the gate dielectric layer. Other non-gate-covered portions of the channel region are located between the source electrode layer and the gate structure and between the drain electrode layer and the gate structure. The FET includes a stoichiometrically oxygen-reduced silicon oxide layer contacting the non-gate-covered portions of the channel region, wherein the stoichiometrically oxygen-reduced silicon oxide composition includes SiO.sub.x where x has a value of less than 2.

The present invention relates to new semiconducting compounds having at least one optionally substituted dithieno[1,2,3]thiadiazole moiety. The compounds disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.

The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a D.sub.it of about 5e.sup.10 cm.sup.?2 eV.sup.?1 to about 5e.sup.11 cm.sup.?2 eV.sup.?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

A method of making a mobile ion regulated device includes stacking a dielectric layer on a substrate. Mobile ions are placed within the dielectric layer. An electrode layer is provided on the dielectric layer. The mobile ions are directed to a designated area of the dielectric layer.

A crosslinked self-assembled monolayer (SAM), comprising surface groups containing a nitrogen-heterocycle, was formed on an oxygen plasma-treated silicon oxide or hafnium oxide top surface of a substrate. The SAM is covalently bound to the underlying oxide layer. The SAM was patterned by direct write methods using ultraviolet (UV) light of wavelength 193 nm or an electron beam, forming a line-space pattern comprising non-exposed SAM features. The non-exposed SAM features non-covalently bound DNA-wrapped carbon nanotubes (DNA-CNT) deposited from aqueous solution with a selective placement efficiency of about 90%. Good alignment of carbon nanotubes to the long axis of the SAM features was also observed. The resulting patterned biopolymer features were used to prepare a CNT based field effect transistor.

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a D.sub.it of about 5e.sup.10 cm.sup.?2eV.sup.?1 to about 5e.sup.11 cm.sup.?2eV.sup.?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.