The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (1C), (1D), (1E) and (1F), wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7 and R.sup.8 are independently and at each occurrence H or C.sub.1-C.sub.10-alkyl.

##STR00001##

Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

The present invention relates to a nanoelectronic device, comprising a substrate layer (10), a first electrode layer (12) disposed on the substrate layer (10), a dielectric layer (16) disposed on the first electrode layer (12), a second electrode layer (18) disposed on the dielectric layer (16), wherein the dielectric layer (16) and the second electrode layer (18) are dimensioned such that at least one protruding portion (18a, 18b) of the second electrode layer (18) is formed in which the second electrode layer (18) extends beyond the dielectric layer such that opposing faces of the first and second electrode are formed (16), at least one semiconductor layer (20) disposed between the first electrode layer (12), one of the protruding portions (18a, 18b) of the second electrode layer (18) and the dielectric layer (16); and a gating arrangement (22) in contact with at least the semiconductor layer (20) as well as the first (12) and second (18) electrode layers.

The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (1C), (1D), (1E) and (1F), wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7 and R.sup.8 are independently and at each occurrence H or C.sub.1-C.sub.10-alkyl. ##STR00001##

Printable and stretchable thin-film devices and fabrication techniques are provided for forming fully-printed, intrinsically stretchable thin-film transistors and integrated logic circuits using stretchable elastomer substrates such as polydimethylsiloxane (PDMS), semiconducting carbon nanotube network as channel, unsorted carbon nanotube network as source/drain/gate electrodes, and BaTiO.sub.3/PDMS composite as gate dielectric. Printable stretchable dielectric layer ink may be formed by mixing barium titanate nanoparticle (BaTiO.sub.3) with PDMS using 4-methyl-2-pentanone as solvent.

A charge trapping non-volatile organic memory device according to the present invention has a structure in which an organic matter-based blocking layer, a trapping layer, and a tunneling layer are sequentially positioned between a gate and an organic semiconductor layer positioned on an insulating substrate, the trapping layer including a metal oxide and a polymer, and has an organic-inorganic composite film in which the metal oxide is dispersed in a polymer matrix in units of atoms.

A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

A field-effect transistor including at least: a substrate; a source electrode; a drain electrode; a gate electrode; a semiconductor layer in contact with the source electrode and with the drain electrode; and a gate insulating layer insulating between the semiconductor layer and the gate electrode, wherein the semiconductor layer contains a carbon nanotube, and the gate insulating layer contains a polymer having inorganic particles bound thereto. Provided is a field-effect transistor and a method for producing the field-effect transistor, wherein the field-effect transistor causes decreased leak current and furthermore enables a semiconductor solution to be uniformly applied.