H01L21/02013

Method for polishing silicon substrate and polishing composition set
11648641 · 2023-05-16 · ·

Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry P.sub.F to the silicon substrate. The total amount of the final stock polishing slurry P.sub.F supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 μg or less.

MANUFACTURING PROCESS OF WAFER THINNING

A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.

INDIUM PHOSPHIDE SUBSTRATE, METHOD OF INSPECTING INDIUM PHOSPHIDE SUBSTRATE, AND METHOD OF PRODUCING INDIUM PHOSPHIDE SUBSTRATE

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

METHOD FOR MANUFACTURING A BONDED SOI WAFER

Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.

MANUFACTURING METHOD FOR A SUBSTRATE WAFER
20230173633 · 2023-06-08 · ·

A manufacturing method for a substrate wafer, including: a wafer having a first and second main surface; forming a flattening resin layer on second main surface; with the flattening resin layer adsorbed and held as a reference surface, grinding or polishing first main surface as a first processing; removing flattening resin layer from the wafer; with the wafer's first main surface subjected to the first processing adsorbed and held, grinding or polishing second main surface as a second processing; with the second main surface subjected to second processing adsorbed and held, further grinding or polishing first main surface as a third processing; with first main surface subjected to third processing adsorbed and held, further grinding or polishing second main surface as a fourth processing to obtain a substrate wafer, wherein first processing and/or third processing is executed such that the wafer has a central concave or central convex thickness distribution.

WAFER PRODUCTION METHOD AND WAFER PRODUCTION MACHINE
20230178358 · 2023-06-08 ·

A wafer production method includes forming, in an ingot, a separating layer that includes modified portions and cracks, by relatively moving the ingot and a focal point of a laser beam, with the focal point positioned at a depth corresponding to a thickness of the wafer, separating the wafer from the ingot by using the separating layer as a separation starting interface, bonding an adhesive tape to at least one of a separated surface of the wafer and a resulting fresh end surface of the ingot, removing separation debris stuck on the at least one surface, by separating the adhesive tape from the at least one surface, and grinding the at least one surface from which the separation debris has been removed. A wafer production machine is also disclosed.

WAFER MANUFACTURING METHOD AND GRINDING APPARATUS
20230178359 · 2023-06-08 ·

In both a case where a workpiece is a regular workpiece having a first residual peeling layer on one surface thereof and a case where the workpiece is an adjustment workpiece not having the first residual peeling layer, a wafer having a predetermined thickness is manufactured by grinding opposite surfaces of the workpiece. That is, in the present invention, because the opposite surfaces of the workpiece are ground, wafers can be manufactured from two kinds of workpieces irrespective of whether or not the first residual peeling layer is present on the one surface of the workpiece. Hence, even when two kinds of workpieces are housed in a mixed manner in a first cassette, wafers having the predetermined thickness can be manufactured easily from these workpieces.

Semiconductor Device and Methods for Forming a Plurality of Semiconductor Devices

A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.

WAFER PROCESSING METHOD
20170330799 · 2017-11-16 ·

A wafer processing method includes a modified layer forming step of applying a laser beam so as to focus the laser beam inside the wafer, and form a modified layer along each division line, a wafer supporting step of attaching an expandable dicing tape to the back side of the wafer and mounting the peripheral portion of the dicing tape to an annular frame before or after performing the modified layer forming step, a tape expanding step of expanding the dicing tape attached to the back side of the wafer, and an air blowing step of blowing air against the wafer in the condition where the dicing tape is expanded, thereby dividing the wafer into individual device chips along each division line where the modified layer is formed and also increasing the spacing between any adjacent ones of the device chips.

Method for manufacturing backside metalized compound semiconductor wafer

A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.