Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle θ on the main surface side of 0°<θ≤110° for all of the planes A where a distance from the main surface is 100 μm or more and 200 μm or less, wherein the angle θ is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature R.sub.f of from 200 to 350 μm.

Provided are abrasive grains, an evaluation method and a wafer manufacturing method. A predetermined amount of abrasive grains is prepared as an abrasive grain sample group, the grain diameter of individual abrasive grains in the abrasive grain sample group is measured, the number of abrasive grains in the abrasive grain sample group as a whole is counted, abrasive grains having a grain diameter equal to or smaller than a predetermined reference grain e diameter criterion which is smaller than the average grain diameter of the abrasive grain sample are defined as small grains and the number of the small grains is counted, a small grain ratio is calculated as the number ratio of the small grains occupied in the abrasive grain sample group as a whole, and a determination is made as to whether or not the small grain ratio is equal to or smaller than a predetermined threshold value.

Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A method for manufacturing a wafer product, including the steps of: chamfering a circumferential edge portion of a wafer; lapping or double-side grinding main surfaces thereof; etching; mirror-polishing the main surface; and mirror-polishing the chamfered portion. The chamfered portion has a cross-sectional shape including: a first inclined portion continuous from the first main surface; a first arc portion continuous from the first inclined portion and having a radius of curvature; a second inclined portion continuous from the second main surface; a second arc portion continuous from the second inclined portion and having a radius of curvature; and an end portion connecting the first arc portion to the second arc portion. This provides a method for manufacturing a wafer by which a variation in a chamfered cross-sectional shape in a circumferential direction caused by etching can be suppressed.

A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

A method, apparatus, and system for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

The present invention provides an aluminum nitride wafer and a method for making the same. The method includes forming at least one alignment notch in or at least one flat alignment edge on a periphery of the aluminum nitride wafer. The alignment notch and the flat alignment edge can prevent the aluminum nitride wafer from being in a poor state during the semiconductor manufacturing process and makes it possible to position the aluminum nitride wafer precisely so that the fraction defective can be lowered. The aluminum nitride wafer of the present invention has advantages of effective insulation, efficient heat dissipation, and a high dielectric constant, and can be used in semiconductor manufacturing processes, electronic products, and semiconductor equipment.

An information processing apparatus is an information processing apparatus that determines a polishing recipe based on area response data acquired by changing a pressure for each area in a polishing head, the apparatus including an irregularity-presence-or-absence estimation unit that estimates and outputs whether an irregularity is present using new area response data as an input, a screening unit estimates and outputs, when the irregularity-presence-or-absence estimation unit estimates that an irregularity is present, area response data after the removal of the irregularity using area response data estimated that an irregularity is present as an input, and a simulation unit that determines a polishing recipe by simulation based on area response data estimated by the irregularity-presence-or-absence estimation unit that no irregularity is present or a response for each area after the removal of the irregularity estimated by the screening unit.

The superior electronic and mechanical properties of 2D-layered transition metal dichalcogenides and other 2D layered materials could be exploited to make a broad range of devices with attractive functionalities. However, the nanofabrication of such layered-material-based devices still needs resist-based lithography and plasma etching processes for patterning layered materials into functional device features. Such patterning processes lead to unavoidable contaminations, to which the transport characteristics of atomically-thin layered materials are very sensitive. More seriously, such lithography-introduced contaminants cannot be safely eliminated by conventional material wafer cleaning approaches. This disclosure introduces a rubbing-induced site-selective growth method capable of directly generating few-layer molybdenum disulfide device patterns without the need of any additional patterning processes. This method consists of two critical steps: (i) a damage-free mechanical rubbing process for generating microscale triboelectric charge patterns on a dielectric surface, and (ii) site-selective deposition of molybdenum disulfide or the like within rubbing-induced charge patterns.