H01L21/02013

FABRICATING A SILICON CARBIDE AND NITRIDE STRUCTURES ON A CARRIER SUBSTRATE

A method, apparatus, and system for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

Method of manufacture including polishing pad monitoring method and polishing apparatus including polishing pad monitoring device

In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height.

Semiconductor Device and Method of Forming Same

A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Wafer processing with a protective film and peripheral adhesive
11784138 · 2023-10-10 · ·

A wafer having on one side a device area with a plurality of devices is processed by providing a protective film and applying the protective film, for covering the devices on the wafer, to the one side of the wafer, so that a front surface of the protective film is in direct contact with the one side of the wafer. The protective film is heated during and/or after applying the protective film to the one side of the wafer, so that the protective film is attached to the one side of the wafer, and the side of the wafer opposite to the one side is processed. Further, the invention relates to a method of processing such a wafer in which a liquid adhesive is dispensed only onto a peripheral portion of a protective film and/or only onto a peripheral portion of the wafer.

Seed crystal for single crystal 4H—SiC growth and method for processing the same

A seed crystal for single crystal 4H-SiC growth of the present invention is a disk-shaped seed crystal for single crystal 4H-SiC growth having a diameter of more than 150 mm and having a thickness within a range of more than or equal to 1 mm and less than or equal to 0.03 times of the diameter, in which one surface on which the single crystal 4H-SiC is grown is a mirror surface and an Ra of the other surface is more than 10 nm, and an absolute value of magnitude of waviness in a state where the seed crystal is freely deformed so that an internal stress distribution is reduced is less than or equal to 12 μm.

MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE

A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

ORIGIN DETERMINATION METHOD AND GRINDING MACHINE
20230321790 · 2023-10-12 ·

An origin determination method includes the steps of adjusting a positional relation between a chuck table and a grinding unit by a moving mechanism such that lower ends of grinding stones and a holding surface are brought apart along a moving direction, moving the chuck table and the grinding unit relative to each other by the moving mechanism such that the lower ends of the grinding stones and the holding surface are brought closer to each other by a predetermined distance, and determining whether a measurement value of a load applied to the holding surface has reached a threshold. If the measurement value is determined to have reached the threshold, a positional relation between the chuck table and the grinding unit at that time is determined to be an origin of the moving mechanism. Otherwise, the step of moving and the step of determining are then performed again.

Substrate processing system for removing peripheral portion of substrate, substrate processing method and computer readable recording medium thereof
11752576 · 2023-09-12 · ·

A substrate processing system configured to process a substrate includes a modification layer forming apparatus configured to form a modification layer within the substrate along a boundary between a peripheral portion of the substrate to be removed and a central portion of the substrate; and a periphery removing apparatus configured to remove the peripheral portion starting from the modification layer.

Method for creating cavities in silicon carbide and other semiconductor substrates

A method for creating at least one cavity in a semiconductor substrate including the steps of: (a) partially ablating the semiconductor substrate from the top side with a laser to form a trench in the semiconductor substrate surrounding a cross section of the semiconductor material having the desired shape, (b) machining the backside of the semiconductor substrate partially ablated in step (a) to reduce the semiconductor substrate to a final thickness that is equal to or less than the laser ablation depth to form a plug of semiconductor material unattached to a remainder of the semiconductor substrate; and (c) removing the plug of semiconductor material from the semiconductor substrate to form the at least one cavity with cross section of desired shape extending through the semiconductor substrate.

Bonded semiconductor devices having processor and static random-access memory and methods for forming the same
11659702 · 2023-05-23 · ·

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.