A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.

One or more embodiments are directed to methods of removing a sacrificial layer from semiconductor wafers during wafer processing. In at least one embodiment, the sacrificial layer is removed from a wafer during an O.sub.2 plasma etch step. In one embodiment, the sacrificial layer is poly(p-phenylene-2, 6-benzobisoxazole) (PBO) or polyimide. The O.sub.2 plasma etch step causes a residue to form on the wafer. The residue is removed by immersing the wafer a solution that is a mixture of the tetramethylammonium hydroxide (TMAH) and water.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.

Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle θ on the main surface side of 0°<θ≤110° for all of the planes A where a distance from the main surface is 100 μm or more and 200 μm or less, wherein the angle θ is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature R.sub.f of from 200 to 350 μm.

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.