A processing method for a wafer having a chamfered portion on an outer circumference thereof includes a step of irradiating a laser beam of a transmission wavelength to the wafer along an outer circumferential edge of the wafer at a position on an inner side of a predetermined distance from the outer circumferential edge of the wafer to form an annular modified region having a depth from a front face of the wafer to a finish thickness, a step of irradiating a laser beam of a transmission wavelength to the wafer on an outer circumferential portion of the wafer to radially form a plurality of modified regions having the depth from the front face of the wafer to the finish thickness on the outer circumferential portion of the wafer, and a step of grinding a back face of the wafer to thin the wafer to the finish thickness.

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

The invention relates to methods of processing a wafer, having on one side a device area with a plurality of devices. In particular, the invention relates to a method which comprises providing a protective film, and applying the protective film to the side of the wafer being opposite to the one side, so that at least a central area of a front surface of the protective film is in direct contact with the side of the wafer being opposite to the one side. The method further comprises applying an external stimulus to the protective film during and/or after applying the protective film to the side of the wafer being opposite to the one side, so that the protective film is attached to the side of the wafer being opposite to the one side, and processing the one side of the wafer and/or the side of the wafer being opposite to the one side.

A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.

A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer.

Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

A method of processing a semiconductor wafer is provided. The method includes providing a semiconductor wafer having a front side and a back side, the semiconductor wafer provided with a circuit layer at the front side and a patterned surface at the back side, forming a sacrificial layer on the back side, mounting a tape on the sacrificial layer, the sacrificial layer isolating the patterned surface from the tape, wherein adhesion strength between the sacrificial layer and the patterned surface is larger than that between the sacrificial layer and the tape, dicing the semiconductor wafer at the back side through the tape, defining individual chips on the semiconductor wafer, and expanding the tape to separate the chips from each other.

Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.