Provided is a method of double-side polishing a silicon wafer using a double-side polishing apparatus, the method including in succession: a first polishing step of performing double-side polishing while supplying a first polishing agent that is an alkaline aqueous solution containing abrasive grains to the polishing cloths; a polishing agent switching step of stopping the supply of the first polishing agent and starting the supply of a second polishing agent that is an alkaline aqueous solution containing a water-soluble polymer with no abrasive grains, with the polishing cloths of the upper plate and the lower plate being in contact with the front surface and the back surface of the silicon wafer, respectively and with the upper plate and the lower plate being continuously rotated; and a second polishing step of performing double-side polishing while supplying the second polishing agent to the polishing cloths.

The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from 1.0 m to 1.0 m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm.sup.2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm.sup.2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm.sup.2 or higher.

A method of processing a wafer includes a grinding step of grinding a reverse side of a wafer that has first insulating films covering via electrodes, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by supplying a first etching gas turned to a plasma, an insulating film forming step of covering the reverse side with a second insulating film, a via electrode exposing step of supplying a second etching gas turned to a plasma to expose the via electrodes after having formed a resist film having openings overlapping the via electrodes, and an electrode forming step of forming electrodes connected to the via electrodes.

A processing method for a wafer having a chamfered portion on an outer circumference thereof includes a step of irradiating a laser beam of a transmission wavelength to the wafer along an outer circumferential edge of the wafer at a position on an inner side of a predetermined distance from the outer circumferential edge of the wafer to form an annular modified region having a depth from a front face of the wafer to a finish thickness, a step of irradiating a laser beam of a transmission wavelength to the wafer on an outer circumferential portion of the wafer to radially form a plurality of modified regions having the depth from the front face of the wafer to the finish thickness on the outer circumferential portion of the wafer, and a step of grinding a back face of the wafer to thin the wafer to the finish thickness.

One or more embodiments are directed to methods of removing a sacrificial layer from semiconductor wafers during wafer processing. In at least one embodiment, the sacrificial layer is removed from a wafer during an O.sub.2 plasma etch step. In one embodiment, the sacrificial layer is poly(p-phenylene-2, 6-benzobisoxazole) (PBO) or polyimide. The O.sub.2 plasma etch step causes a residue to form on the wafer. The residue is removed by immersing the wafer a solution that is a mixture of the tetramethylammonium hydroxide (TMAH) and water.

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation 1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including aurum on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by physical vapor deposition on the backside of the bowed semiconductor substrate in regions to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve sputtering material onto a backside of a substrate using a shadow mask or by using more than one target and rotating the semiconductor substrate being sputtering operations.

Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).