A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.

A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the principal surfaces, and the mirror-polishing of the outer-periphery chamfered portion in this order.

An as-sliced wafer processing method includes a grinding step of grinding a first surface of an as-sliced wafer, an outer periphery positioning step of moving a chuck table and a grinding unit relative to each other in directions parallel to a holding surface of the chuck table so as to position an edge on an outer periphery of grinding stones at an outer peripheral edge of the first surface after the grinding step is carried out, and a chamfering step of chamfering an outer periphery of the first surface of the as-sliced wafer by the grinding stones after the outer periphery positioning step is carried out.

Provided is an indium phosphide substrate, a method for manufacturing indium phosphide substrate, and a semiconductor epitaxial wafer capable of suppressing an occurrence of contamination of the surface of the indium phosphide substrate caused by residues at the edge part. An indium phosphide substrate, wherein a surface roughness of an edge part of the substrate has a root mean square height Sq of 0.15 μm or less, as measured by a laser microscopy on the entire surface of the edge part.

A highly thermal conductive substrate formed by bonding a device layer formed on a silicon on insulator (SOI) wafer and a buried oxide film to an insulator substrate having a thermal conductivity of 40 W/m.Math.K or more via a low-stress adhesive, wherein a thickness of the buried oxide film is 50 to 500 nm and a thickness of the adhesive is 0.1 to 10 μm.

Provided is a method of chamfer machining a silicon wafer which makes it possible to increase the number of machining operations that can be performed using a chamfering wheel used for helical chamfer machining in the case of obtaining a small finished wafer taper angle. The method in which helical chamfer machining is performed so that the finished wafer taper angle θ of an edge portion in the one silicon wafer is within an allowable angle range of a target wafer taper angle θ.sub.0 includes a first truing step; a first chamfer machining step; a step of determining a groove bottom diameter ϕ.sub.A of the fine grinding grindstone portion; a second truing step using a second truer taper angle α.sub.2; and a second chamfer machining step. The second truer taper angle α.sub.2 is made larger than the first truer taper angle α.sub.1.

The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.

A semiconductor substrate includes a gallium oxide-based semiconductor single crystal and a chamfered portion at an outer periphery portion. The chamfered portion includes a first inclined surface located on the outer side of a first principal surface of the semiconductor substrate and being linear at an edge in a vertical cross section of the semiconductor substrate, a second inclined surface located on the outer side of a second principal surface on the opposite side to the first principal surface and being linear at an edge in the vertical cross section, and an end face located between the first inclined surface and the second inclined surface at a leading end of the chamfered portion. A width of the end face in a thickness direction of the semiconductor substrate is within the range of not less than 50% and not more than 97% of a thickness of the semiconductor substrate.

An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method.

The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.

A monocrystalline semiconductor wafers have an average roughness R.sub.a of at most 0.8 nm at a limiting wavelength of 250 μm, and an ESFQR.sub.avg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.