A method of transferring a device layer in a SOI wafer obtained by stacking a Si layer, an insulator layer, and the device layer to a transfer substrate, includes a step of temporarily bonding a surface on which the device layer is formed of the SOI wafer to a supporting substrate using an adhesive for temporary bonding, a step of removing the Si layer of the SOI wafer until the insulator layer is exposed and obtaining a thinned device wafer, a step of coating only the transfer substrate with an adhesive for transfer and then bonding the insulator layer in the thinned device wafer to the transfer substrate via the adhesive for transfer, a step of thermally curing the adhesive for transfer under a load at the same time as or after bonding, a step of peeling off the supporting substrate, and a step of removing the adhesive.

A substrate processing system configured to process a substrate includes an eccentricity detection device configured to detect, in a combined substrate in which a first substrate and a second substrate are bonded to each other, an eccentricity of the first substrate; a modification layer forming device configured to form a modification layer within the first substrate along a boundary between a peripheral portion to be removed and a central portion of the first substrate; and a periphery removing device configured to remove the peripheral portion starting from the modification layer.

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.

Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. The silicon carbide substrate (100) comprises a main surface (102) and a circumferential end face surface (114) which is essentially perpendicular to the main surface (102), and a chamfered peripheral region (110), wherein a first bevel surface (106) of the chamfered peripheral region (110) includes a first bevel angle (a1) with said main surface (102), and wherein a second bevel surface (108) of the chamfered peripheral region (110) includes a second bevel angle (a2) with said end face surface (114), wherein, in more than 75% of the peripheral region, said first bevel angle (a1) has a value in a range between 20° and 50°, and said second bevel angle (a2) has a value in a range between 45° and 75°.

The present invention provides an aluminum nitride wafer and a method for making the same. The method includes forming at least one alignment notch in or at least one flat alignment edge on a periphery of the aluminum nitride wafer. The alignment notch and the flat alignment edge can prevent the aluminum nitride wafer from being in a poor state during the semiconductor manufacturing process and makes it possible to position the aluminum nitride wafer precisely so that the fraction defective can be lowered. The aluminum nitride wafer of the present invention has advantages of effective insulation, efficient heat dissipation, and a high dielectric constant, and can be used in semiconductor manufacturing processes, electronic products, and semiconductor equipment.

According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

An electrolytic plating apparatus includes a plating tank that is filled with plating liquid; a moving mechanism configured to vertically move a processing target substrate in a direction normal to a surface of the plating liquid; a seal member that is disposed at a peripheral edge portion of a processing target surface of a processing target substrate and is configured to seal the plating liquid to a center side of the processing target surface when the processing target substrate is immersed in the plating tank; and a contact member that is separated from the seal member and is electrically connected to the processing target surface.