Patent classifications
H01L21/02024
SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE
A silicon carbide substrate is a silicon carbide substrate including: a first main surface, a shape of the first main surface before the orientation flat is provided being a circle. An average value of LTVs of a plurality of first square regions of a plurality of square regions is less than or equal to 0.75 μm, the plurality of first square regions being disposed in a form of a ring on an outermost side with respect to the center of the circle so as to form an outermost periphery when the central region of the first main surface is divided into the plurality of square regions to provide a largest number of square regions, each of the square regions exactly forming a square having each side of 5 mm.
POLISHING COMPOSITION
The polishing composition provided by the present invention contains an abrasive, a polyvinyl alcohol polymer as a water-soluble polymer, a basic compound, and water, and further contains a trivalent or higher polyvalent organic acid (salt).
POLISHING HEAD, POLISHING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR WAFER
A polishing head includes a first ring-shaped member having an opening; a plate-shaped member that closes the opening on an upper side of the first ring-shaped member; a membrane that closes the opening on a lower side of the first ring-shaped member; a back pad adhered to a lower surface of the membrane; and a second ring-shaped member located below the back pad and having an opening that holds a polishing target workpiece. A space formed by closing the opening of the first ring-shaped member by the plate-shaped member and the membrane includes: a central region; and an outer peripheral region partitioned from the central region by a partition, and an inner peripheral edge region of the second ring-shaped member is located vertically below an outer peripheral edge of the outer peripheral region. A polishing apparatus includes the polishing head, and is used in a method of manufacturing a semiconductor wafer.
Polishing liquid and polishing method
A polishing liquid is provided containing manganese oxide abrasive grains, permanganate ions, and a cellulosic surfactant or a cationic surfactant. The polishing liquid has a pH of 5 or more and 11 or less. The cellulosic surfactant is preferably a carboxymethyl cellulose or a derivative thereof. The cationic surfactant preferably has a quaternary ammonium ion site. The content of the cellulosic surfactant or the cationic surfactant is preferably 0.01 mass % or more and 1.0 mass % or less based on the total amount of the polishing liquid.
Polishing composition
The present invention provides a polishing composition with which polishing rates can be effectively improved and which is for polishing works to be polished. The polishing composition comprises water, abrasive grains, an oxidant, and a polishing accelerator. The polishing accelerator comprises at least one metal salt selected from the group consisting of alkali metal salts and alkaline-earth metal salts.
Polishing composition and polishing method using same
The present invention relates to a polishing composition containing an abrasive, a water-soluble polymer, an anionic surfactant, a basic compound, and water, in which the anionic surfactant has an oxyalkylene unit, and an average addition mole number of the oxyalkylene unit of the anionic surfactant is more than 3 and 25 or less. According to the present invention, it is possible to provide a polishing composition which can reduce the haze of a polished object and is also excellent in a polishing removal rate.
SYSTEMS AND METHODS FOR PRODUCING EPITAXIAL WAFERS
A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.
Method of double-side polishing semiconductor wafer
Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.
Double-side polishing method and double-side polishing apparatus
A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0≤A+B≤2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.
Polishing composition
Provided is a polishing composition that can effectively improve a polishing removal rate. According to the present invention, a polishing composition for polishing a polishing target material is provided. The polishing composition contains water, an oxidant, and a polishing removal accelerator, and does not contain abrasive. At least one metal salt selected from the group consisting of an alkali metal salt and an alkaline earth metal salt is contained as the polishing removal accelerator.