Patent classifications
H01L21/02123
Tri-axial MEMS accelerometer
A tri-axial MEMS accelerometer includes a top cap silicon wafer and a bottom cap silicon wafer coupled with a measurement mass. The measurement mass has a two level structure, each level having an inner frame coupled to an outer frame by a plurality of first elastic beams, a mass coupled to the inner frame by a plurality of second elastic beams, and a comb coupling structure between the mass and the inner frame. The comb coupling structures are arranged in an orthogonal orientation. The top level and bottom level measurement masses measure acceleration in perpendicular directions. The top level and bottom level measurement masses and the inner frame form an integral unit which moves along a third direction. Acceleration in the third direction is measured from the change in capacitance between the integral unit and the top cap silicon wafer and bottom cap silicon wafer.
Self-aligned double spacer patterning process
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask.
FILM-FORMING COMPOSITION
A composition for forming a film capable of effectively functioning as a resist underlayer film exhibiting resistance to a solvent in a composition for forming a resist film serving as an upper layer, favorable etching property to a fluorine-containing gas, and favorable lithographic property. A film-forming composition including a hydrolysis condensate prepared through hydrolysis and condensation of a hydrolyzable silane compound by using two or more acidic compounds, and a solvent, the film-forming composition being characterized in that: the hydrolyzable silane compound contains an amino-group-containing silane of the following Formula (1):
R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4−(a+b) (1)
METHOD FOR PRODUCING CHLORINATED OLIGOSILANES
The present invention relates to a process for preparing chlorinated oligosilanes, wherein chlorinated polysilane having an empirical formula of SiCl.sub.1.0-2.8 and/or a mixture comprising the chlorinated polysilane is reacted with elemental chlorine or a chlorine-containing mixture. Additionally claimed are chlorinated oligosilanes prepared by the process and the use thereof for production of semiconductors and/or hard coatings.
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.
Method and Structure for FinFET Device
The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
Chemical vapor deposition process and coated article
Chemical vapor deposition processes and coated articles are disclosed. The process includes a first introducing of a first amount of silane to the enclosed chamber, the first amount of the silane remaining within the enclosed chamber for a first period of time, a first decomposing of the first amount of the silane during at least a portion of the first period of time, a second introducing of a second amount of the silane to the enclosed chamber, the second amount of the silane remaining within the enclosed chamber for a second period of time, and a second decomposing of the second amount of the silane during at least a portion of the second period of time. The process is devoid of inert gas purging between the first decomposing and the second introducing and/or produces a chemical vapor deposition coating devoid of hydrogen bubbles.
HIGH RESISTIVITY SINGLE CRYSTAL SILICON INGOT AND WAFER HAVING IMPROVED MECHANICAL STRENGTH
A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
CARBOSILANE SUBSTITUTED AMINE PRECURSORS FOR DEPOSITION OF Si-CONTAINING FILMS AND METHODS THEREOF
Disclosed are Si-containing film forming compositions comprising carbosilane substituted amine precursors. The carbosilane substituted amine precursors have the formula (R.sup.1).sub.aN(—SiHR.sup.2—CH.sub.2—SiH.sub.2R.sup.3).sub.3-a, wherein a=0 or 1; R.sup.1 is H, a C1 to C6 alkyl group, or a halogen; R.sup.2 and R.sup.3 is each independently H; a halogen; an alkoxy group having the formula OR′, wherein R′ is an alkyl group (C1 to C6); or an alkylamino group having the formula NR″.sub.2, wherein each R″ is independently H, a C1-C6 alkyl group, a C1-C6 alkenyl group, or a C3-C10 aryl or heterocycle group. Also disclosed are methods of synthesizing the carbosilane substituted amine precursors and their use for deposition processes.
ENGINEERED ETCHED INTERFACES FOR HIGH PERFORMANCE JUNCTIONS
Various methods for fabricating a semiconductor device by selective in-situ cleaning of a target surface of a semiconductor substrate by selective dry surface atomic layer etching of the target surface film, selectively removing one or more top layers of atoms from the target surface film of the semiconductor substrate. The selective in-situ cleaning of a target surface can be followed by deposition on the cleaned target surface such as to form a cap layer, a conductive contact layer, or a gate dielectric layer.