Patent classifications
H01L21/02123
HIGH RESISTIVITY SINGLE CRYSTAL SILICON INGOT AND WAFER HAVING IMPROVED MECHANICAL STRENGTH
A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
Semiconductor device and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.
Method of manufacturing semiconductor structure
A method of manufacturing a semiconductor structure includes the following operations. A substrate embedded with a shallow trench isolation is received. A first dielectric layer is formed on the substrate. An etching process is performed to form a hole in the first dielectric layer and form a pit in the substrate, wherein an upper surface of the shallow trench isolation is exposed from the hole, and the pit is adjacent to the shallow trench isolation. A second dielectric layer is formed on the first dielectric layer and the shallow trench isolation and in the pit. The second dielectric layer is treated with a plasma to convert a first portion of the second dielectric layer substantially on the first dielectric layer and the shallow trench isolation to a plasma-treated layer. The plasma-treated layer is removed to remain a second portion of the second dielectric layer in the pit.
Methods of Manufacturing An Integrated Circuit Having Stress Tuning Layer
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
Film forming method and film forming apparatus
A film forming method includes: removing a natural oxide film formed on a front surface of a metal-containing film by supplying a hydrogen fluoride gas to a substrate accommodated in a processing container, the substrate having the metal-containing film formed thereon, and the metal-containing film including no metal oxide film; and forming a silicon film on the metal-containing film by supplying a silicon-containing gas into the processing container, wherein the step of forming the silicon film occurs after the step of removing the natural oxide film.
Semiconductor device pre-cleaning
An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
Treatment to control deposition rate
A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.
Apparatus for atomic layer deposition and method of forming thin film using the apparatus
An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.
Barrier-free approach for forming contact plugs
A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
ORGANIC VAPOR JET PRINTING SYSTEM
Implementations of the disclosed subject matter provide an organic vapor jet print die including a linear array of depositors, with each of the depositors having a cluster of apertures. The organic vapor jet print die may include at least one first aperture in each cluster of apertures is a delivery aperture that is in fluid communication with a carrier gas source and an evaporation oven. At least one second aperture in each cluster of apertures may be an exhaust aperture in fluid communication with a vacuum reservoir with a static pressure lower than that at the apertures. The delivery apertures and exhaust apertures may have a uniformity that is less than 0.4%.