Provided is a resist underlayer film-forming composition for forming resist underlayer film usable as hard mask and removable by wet etching process using chemical solution such as sulfuric acid/hydrogen peroxide. A resist underlayer film-forming composition for lithography includes a component (A) and component (B), the component (A) includes a hydrolyzable silane, hydrolysis product thereof, or hydrolysis-condensation product thereof, the hydrolyzable silane includes hydrolyzable silane of Formula (1): R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4−(a+b) (where R.sup.1 is organic group of Formula (2): ##STR00001##
and is bonded to silicon atom through a Si—C bond; R.sup.3 is an alkoxy group, acyloxy group, or halogen group; is an integer of 1; b is an integer of 0 to 2; and a+b is an integer of 1 to 3), and the component (B) is cross-linkable compound having ring structure having alkoxymethyl group or hydroxymethyl group, cross-linkable compound having epoxy group or blocked isocyanate group.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the oxygen-containing precursor at a temperature less than or about 700° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×10.sup.14 atoms/cm.sup.3 and/or germanium at a concentration of at least about 1×10.sup.19 atoms/cm.sup.3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.