A film forming method includes: removing a natural oxide film formed on a front surface of a metal-containing film by supplying a hydrogen fluoride gas to a substrate accommodated in a processing container, the substrate having the metal-containing film formed thereon, and the metal-containing film including no metal oxide film; and forming a silicon film on the metal-containing film by supplying a silicon-containing gas into the processing container, wherein the step of forming the silicon film occurs after the step of removing the natural oxide film.

The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

A method of forming a composite crystalline nitride structure is provided. The method includes depositing a first crystalline nitride layer on a substrate, patterning the first crystalline nitride layer to form a patterned crystalline nitride layer having a top surface and that includes undulations, annealing the patterned crystalline nitride layer at a temperature between 300° C. to 850° C. to form an annealed patterned crystalline nitride layer, and depositing a second crystalline nitride layer on the annealed patterned crystalline nitride layer. The second crystalline nitride layer is lattice-matched to the underlying annealed patterned crystalline nitride layer to within 2%, thereby forming the composite crystalline nitride structure.

A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Some embodiments include a method of depositing a photoresist onto a substrate in a processing chamber. In an embodiment, the method comprises flowing an oxidant into the processing chamber through a first path in a showerhead, and flowing an organometallic into the processing chamber through a second path in the showerhead. In an embodiment, the first path is isolated from the second path so that the oxidant and the organometallic do not mix within the showerhead. In an embodiment, the method further comprises that the oxidant and the organometallic react in the processing chamber to deposit the photoresist on the substrate.