A wafer may comprise a substrate layer and a plurality of vertical cavity surface emitting lasers (VCSELs) formed on or within the substrate layer. A respective trench-to-trench distance associated with the plurality of VCSELs may vary across the wafer based on a predicted variation of an oxidation rate of an oxidation layer across the wafer.

There is provided a technique that includes: forming an oxide film having a predetermined thickness on a surface of a substrate by performing a cycle a plurality of times, the cycle including non-simultaneously performing: (a) forming a nitride film by supplying a film-forming gas to the substrate; and (b) oxidizing and changing the nitride film into a first oxide film by supplying an oxidizing gas to the substrate, wherein a maximum distance from an interface between the nitride film formed in (a) and a base of the nitride film to a surface of the nitride film is set to 2 nm or more and 4 nm or less.

Embodiments described herein generally relate to conformal oxidation processes for flash memory devices. In conventional oxidation processes for gate structures, growth rates have become too fast, ultimately creating non-conformal films. To create a preferred growth rate for SiO.sub.2 on SiN.sub.x films, embodiments in this disclosure use a thermal combustion of a ternary mixture of H.sub.2+O.sub.2+N.sub.2O to gain SiO.sub.2 out of Si containing compounds. Using this mixture provides a lower growth in comparison with using only H.sub.2 and O.sub.2, resulting in a lower sticking coefficient. The lower sticking coefficient allows an optimal amount of atoms to reach the bottom of the gate, improving the conformality in 3D NAND SiO.sub.2 oxidation layers, specifically for ONO replacement tunneling gate formation.

A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

A gas cleaning method includes: (a) removing a first metal element as one of contaminants from a process chamber by supplying a chlorine-containing gas into the process chamber without supplying an oxygen-containing gas; and (b) removing a second metal element as another one of the contaminants from the process chamber by supplying the oxygen-containing gas into the process chamber, wherein (b) is performed after (a).

A semiconductor structure and a method are provided. The method includes patterning a substrate to form a first fin structure in a first region and a second fin structure in a second region, wherein a first width of the first fin structure is greater than a second width of the second fin structure; forming a protecting layer on the second fin structure; and forming a first oxide layer over the first fin structure and forming a second oxide layer over the protecting layer, wherein a width of the first oxide layer is greater than a width of the second oxide layer.

There is provided a technique that includes: forming a film containing Si, O and N or a film containing Si and O on a substrate by performing a cycle a predetermined number of times under a condition where SiCl.sub.4 is not gas-phase decomposed, the cycle including non-simultaneously performing: (a) forming NH termination on a surface of the substrate by supplying a first reactant containing N and H to the substrate; (b) forming a SiN layer having SiCl termination formed on its surface by supplying the SiCl.sub.4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl.sub.4; and (c) reacting the SiN layer having the SiCl termination with a second reactant containing O by supplying the second reactant to the substrate

A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

The semiconductor device includes interlayer insulating layers, a gate pattern and a vertical memory structure. The interlayer insulating layers are stacked on the substrate to be spaced apart from each other. The gate pattern includes an overlapping portion disposed vertically between the interlayer insulating layers, and an extension portion extending from the overlapping portion in a horizontal direction parallel to an upper surface of the substrate. The vertical memory structure includes a channel semiconductor layer and a dielectric structure, the channel semiconductor layer extends in a direction perpendicular to the substrate upper surface to have side surfaces that face side surfaces of the interlayer insulating layers and a side surface of the extension portion. The dielectric structure is disposed between the channel semiconductor layer and the gate pattern and extends between the channel semiconductor layer and the interlayer insulating layers, and the extension portion has a vertical thickness less than that of the overlapping portion.

A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.