Methods for forming a SiBN film comprising depositing a film on a feature on a substrate. The method comprises in a first cycle, depositing a SiB layer on a substrate in a chamber using a chemical vapor deposition process, the substrate having at least one feature thereon, the at least one feature comprising an upper surface, a bottom surface and sidewalls, the SiB layer formed on the upper surface, the bottom surface and the sidewalls. In a second cycle, the SiB layer is treated with a plasma comprising a nitrogen-containing gas to form a conformal SiBN film.

There is provided a plasma vessel in which a process gas is plasma-excited; a substrate process chamber which is in communication with the plasma vessel; a gas supply system supplying the process gas; and a coil installed to wind around an outer periphery of the plasma vessel and supplied with high-frequency power, wherein the coil is installed such that: a distance from an inner periphery of the coil to an inner periphery of the plasma vessel at a predetermined position on the coil is different from a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at another position on the coil; and a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at a position at which an amplitude of a standing wave of a voltage applied to the coil is maximized is maximized.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.

A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.

Processes and apparatuses for the treatment of semiconductor workpieces are provided. In some embodiments, a method can include placing the workpiece in a processing chamber. The processing chamber can be separated from a plasma chamber by a separation grid assembly. The method can include forming a passivation layer on the workpiece in the processing chamber using radicals generated in a first plasma in the plasma chamber. The method can include performing a surface treatment process on the workpiece in the processing chamber using a second plasma generated in the plasma chamber.