A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is surrounded by the dielectric layer. A metal layer is disposed over the dielectric layer. The second segment of the fin structure is surrounded by the metal layer. The dielectric layer has a greater nitrogen content than the metal layer. The first segment of the fin structure also has a first side surface that is rougher than a second side surface of the second segment of the fin structure.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Embodiments described herein generally relate to a processing chamber having one or more gas inlet ports located at a bottom of the processing chamber. Gas flowing into the processing chamber via the one or more gas inlet ports is directed along a lower side wall of the processing chamber by a plate located over each of the one or more gas inlet ports or by an angled opening of each of the one or more gas inlet ports. The one or more gas inlet ports and the plates may be located at one end of the processing chamber, and the gas flow is directed towards an exhaust port located at the opposite end of the processing chamber by the plates or the angled openings. Thus, more gas can be flowed into the processing chamber without dislodging particles from a lid of the processing chamber.

Methods for forming a SiBN film comprising depositing a film on a feature on a substrate. The method comprises in a first cycle, depositing a SiB layer on a substrate in a chamber using a chemical vapor deposition process, the substrate having at least one feature thereon, the at least one feature comprising an upper surface, a bottom surface and sidewalls, the SiB layer formed on the upper surface, the bottom surface and the sidewalls. In a second cycle, the SiB layer is treated with a plasma comprising a nitrogen-containing gas to form a conformal SiBN film.

A method for manufacturing a semiconductor includes: providing a substrate; forming a polysilicon layer on the substrate, a surface, away from the substrate, of the polysilicon layer having a native oxide; and performing a nitriding treatment to the native oxide, to nitrogenize the native oxide into a silicon oxynitride layer. The native oxide is nitrogenized into the silicon oxynitride layer.

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.