Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

An apparatus includes: a processing container; a stage provided inside the processing container to place a substrate thereon; a gas supply mechanism for supplying a processing gas into the processing container; and at least three ultraviolet light sources provided to irradiate the processing gas inside the processing container with ultraviolet rays. The ultraviolet light sources are provided to be offset from a rotation axis of the stage in a plan view, and are arranged in a light source arrangement direction with distances from the ultraviolet light sources to the rotation axis being different from one another. The ultraviolet light sources include first to third ultraviolet light source. The third ultraviolet light source is arranged such that distances L1, L2, and L3 from the first to third ultraviolet light sources, respectively, to the rotation axis in a plan view satisfies a relationship of L1<L3<L2.

Apparatus, systems, and methods for processing workpieces are provided. In one example implementation, a hydrogen gas mixed with an inert gas can be reacted with an oxygen gas to oxidize a workpiece at atmospheric pressure. A chemical reaction of a hydrogen gas with an oxygen gas facilitated by a hot workpiece surface can positively affect an oxidation process. A reaction speed of the chemical reaction can be slowed down by mixing the hydrogen gas with an inert gas. Such mixture can effectively reduce a partial pressure of the hydrogen gas. As such, the oxidation process can be carried out at atmospheric pressure, thereby, in an atmospheric thermal processing chamber.

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.