A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

Provided is a method of manufacturing a semiconductor device capable of suppressing variation in thickness of oxide films among a plurality of SiC wafers. Forming first inorganic films on lower surfaces of a plurality of SiC wafer, and then performing etching of the plurality of SiC wafers so that 750 nm or more of the first inorganic film is left in thickness, and then forming oxide films on upper surfaces of the plurality of SiC wafers by performing thermal oxidation treatment in a state in which a first SiC wafer of the plurality of SiC wafers is placed directly below any one of at least one wafer, including at least one of a dummy wafer and a monitor wafer, and a second SiC wafer of the plurality of SiC wafers is placed directly below a third SiC wafer of the plurality of SiC wafers.

A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Provided is a semiconductor device including a semiconductor substrate having a first dopant of a first conductivity type and a second dopant of a second conductivity type, both the first dopant and the second dopant being distributed in an entire part of the semiconductor substrate, the semiconductor substrate including a drift region of the first conductivity type, a dielectric film provided on an upper surface of the semiconductor substrate, a high concentration region of the first conductivity type provided in contact with the dielectric film below the dielectric film and having a higher doping concentration than the drift region, and a fall off region that is provided in contact with the dielectric film below the dielectric film and in which a concentration of the dopant of the second conductivity type decreases toward the dielectric film.

Provided are a layer structure including a carbon-based material, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure may include a lower layer, an ion implantation layer in the lower layer, and a carbon-based material layer on the ion implantation layer, wherein the ion implantation layer includes carbon. The ion implantation layer may include a trench, and the carbon-based material layer may be provided in the trench. The carbon-based material layer may be formed to coat an inner surface of the trench. The carbon-based material layer may fill at least a portion of the trench. The ion implantation concentration of the ion implantation layer may be uniform as a whole. The ion implantation layer may have an ion implantation concentration gradient in a given direction.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.

A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.