A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).

According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.

A method includes holding a semiconductor substrate by a substrate holder of an electrochemical apparatus. The electrochemical apparatus includes a reaction cell and a counter electrode, and the semiconductor substrate has an exposed surface containing germanium, silicon, silicon germanium or any of III-V elements. The exposed surface of the semiconductor substrate is immersed in an electrolyte bath in the reaction cell. A portion of the semiconductor substrate is removed by supplying a first current to the counter electrode and a second current to the semiconductor substrate. The second current has a negative bias. The negative bias is smaller than 0V and equal to or larger than minus 5V.

A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.

A thin-film transistor (TFT) and a manufacturing method thereof. The manufacturing method for the TFT includes: depositing metal film layers on a substrate by a direct current (DC) sputtering method; and forming a metal oxide film layer or metal oxide film layers by completely oxidizing or partially oxidizing the metal film layers. The TFT includes a gate electrode layer and a gate insulating layer which are tightly integrated.

A method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate, and a display device are provided. The method for manufacturing the thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the surface of the active layer; and processing the metal layer using a patterning process for one time and an oxidation treatment process, so that the metal layer forms a source electrode, a drain electrode and a passivation layer; wherein the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer.

A seed layer of aluminum is deposited over a wafer. A layer of photoresist material is deposited over the seed layer of aluminum. The photoresist material is patterned and developed to expose portions of the seed layer of aluminum through openings in the photoresist material. An electrochemical transformation process is performed on the wafer to electrochemically transform the portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide (AAO). The AAO includes a pattern of holes that extend through the AAO to expose areas of the top surface of the wafer beneath the seed layer of aluminum. The photoresist material is removed from the wafer. The wafer is exposed to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the AAO.

A method of manufacturing an integrated device that includes: forming, on a substrate, a metal anodization barrier layer; planarizing the metal anodization barrier layer; forming, on the planarized metal anodization barrier layer, an anodizable metal layer; planarizing the anodizable metal layer; and anodizing the planarized anodizable metal layer to obtain an anodic porous oxide region having a plurality of substantially straight pores that extend from a top surface of the anodic porous oxide region towards the metal anodization barrier layer.

A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

A method includes holding a semiconductor substrate by a substrate holder of an electrochemical apparatus. The electrochemical apparatus includes a reaction cell and a counter electrode, and the semiconductor substrate has an exposed surface containing germanium, silicon, silicon germanium or any of III-V elements. The exposed surface of the semiconductor substrate is immersed in an electrolyte bath in the reaction cell. A portion of the semiconductor substrate is removed by supplying a first current to the counter electrode and a second current to the semiconductor substrate. The second current has a negative bias. The negative bias is smaller than 0V and equal to or larger than minus 5V.