A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Embodiments of the invention provide a method for metal filling and planarization of a recessed feature in a substrate. According to one embodiment the method includes providing the substrate containing the recessed feature below a planar surface of the substrate, filling the recessed feature with a metal layer, the metal layer forming excess metal above the recessed feature, oxidizing the excess metal by electrochemical oxidation to form an oxidized metal layer above the planar surface of the recessed feature, and removing the oxidized metal layer by chemical mechanical planarization (CMP). According to another embodiment, the method includes, following the filling, performing a cyclical electrochemical oxidation and etching process that at least substantially removes the excess metal layer above the planar surface of the recessed feature.

A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.

A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

Provided is a long-term implantable electronic device comprising a first thermally oxidized laver from a first substrate, wherein the first thermally oxidized laver forms a first encapsulation laver; an electronic component supported by the first encapsulation laver, wherein the electronic component and the first encapsulation laver have an exposed surface relative to the first encapsulation laver; a barrier laver that covers the first encapsulation laver and the electronic component exposed surface; a second thermally oxidized layer from a second substrate, wherein the second thermally oxidized layer forms a second encapsulation laver, and the second encapsulation laver is in contact with the barrier layer. Each of the first and second encapsulation layers, the barrier layer, and the electronic component are flexible or bendable, so that the long-term implantable electronic device is configured to conformally contact with a curved biological surface.

A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. Additionally, the method includes connecting a carrier substrate to the oxide layer and processing a back side of the semiconductor substrate.

III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.