A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

A method for producing a component without tabs during etching. The method includes: applying a wafer tape to the plated side of the substrate; depositing a resist layer on a metal layer on a metal side of the substrate that is opposite of the plated side; exposing the resist layer to UV light; developing the resist layer; and etching the metal layer.

A method of an etching includes preparing a substrate having a first region formed of silicon oxide and a second region formed of silicon nitride; etching the first region by exposing the substrate to plasma of a first processing gas including a fluorocarbon gas, and forming a deposit including fluorocarbon on the first region and the second region; etching the first region and the second region by radicals of the fluorocarbon included in the deposit; and removing the deposit by plasma of a second processing gas which does not include oxygen.

There is provided a technique that includes: removing a deposit that adheres to an interior of a process chamber by performing a cycle a predetermined number of times, the cycle including performing sequentially: (a) supplying a cleaning gas to the interior of the process chamber until an internal pressure of the process chamber rises to a first pressure range; (b) exhausting the interior of the process chamber and supplying the cleaning gas to the interior of the process chamber in parallel to maintain the internal pressure of the process chamber within the first pressure range; and (c) exhausting the interior of the process chamber until the internal pressure of the process chamber reaches a second pressure that is below the first pressure range.

According to one embodiment, an electronic apparatus including a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including: a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.

The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

Described herein is a technique capable of suppressing a deviation in a thickness of a film formed on a substrate. According to one aspect of the technique of the present disclosure, a substrate processing apparatus includes a substrate retainer capable of supporting substrates; a cylindrical process chamber including a discharge part and supply holes; partition parts arranged in the circumferential direction to partition supply chambers communicating with the process chamber through the supply holes; nozzles provided with an ejection hole; and gas supply pipes. The supply chambers includes a first nozzle chamber and a second nozzle chamber, the process gas includes a source gas and an assist gas, the nozzles includes a first nozzle for the assist gas flows and a second nozzle disposed in the second nozzle chamber and through which the source gas flows, and the first nozzle is disposed adjacent to the second nozzle.

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.

A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.