A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si.sub.1−x−yM1.sub.xM2.sub.y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.

A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide. The silicon carbide semiconductor device has a vacancy trap in an entire area of the semiconductor substrate.

An epitaxial growth device includes; a chamber; a susceptor; a supporting shaft, having a main column located coaxially with the center of the susceptor and supporting arms; and a lift pin, at least the surface layer region of the lift pin is made of a material having a hardness lower than the susceptor, the lift pin has a straight trunk part upper region configured to pass through the through-hole of the susceptor and having a surface roughness of from not less than 0.1 μm to not more than 0.3 μm, and the lift pin has a straight trunk part lower region configured to pass through the through-hole of the supporting arm and having a surface roughness of from not less than 1 μm to not more than 10 μm.

An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

A method for manufacturing a nitride semiconductor substrate by using a vapor phase growth method, including: a step of preparing a base substrate of a single crystal of a group III nitride semiconductor and in which a low index crystal plane closest to a main surface is a (0001) plane; an etching step of the base substrate to roughen the main surface; a first step of growing a first layer by epitaxially growing a single crystal of a group III nitride semiconductor on the main surface, and at least some of the plurality of recessed portions being gradually expanded toward an upper side of the main surface of the base substrate, the first layer including a first surface from which the (0001) plane has disappeared and that is constituted only by the inclined interfaces; and a second step of growing a second layer including a mirror second surface.

Provided are a GaN crystal used in a substrate for a nitride semiconductor device having a horizontal device structure such as GaN-HEMT, and a substrate used for production of a nitride semiconductor device having a horizontal device structure such as GaN-HEMT. The Gab crystal has a (0001) surface having an area of not less than 5 cm.sup.2, the (0001) surface having an inclination of not more than 10° with respect to the (0001) crystal plane, wherein the Fe concentration is not less than 5×10.sup.17 atoms/cm.sup.3 and less than 1×10.sup.9 atoms/cm.sup.3, and wherein the total donor impurity concentration is less than 5×10.sup.16 atoms/cm.sup.3.

A semiconductor device includes a semiconductor substrate that includes an element region and a peripheral withstand voltage region. An insulating protection film is provided above the peripheral withstand voltage region. The peripheral withstand voltage region includes a plurality of guard ring regions of p-type in direct contact with the insulating protection film and a drift region of n-type separating the guard ring regions from each other. Each guard ring region includes a guard ring low concentration region being in direct contact with the insulating protection film and a guard ring high concentration region having a p-type impurity concentration equal to or more than ten times as high as that in the corresponding guard ring low concentration region. Each guard ring high concentration region is provided under the corresponding guard ring low concentration region, and separated from the insulating protection film by the corresponding guard ring low concentration region.

Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.