A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

A substrate processing method for forming fully self-aligned vias. The method may be performed in a batch processing system that is capable of simultaneously processing multiple substrates, where the batch processing system includes a process chamber containing processing spaces defined around an axis of rotation in the process chamber. Each of the substrates contain a first surface and a second surface, and the method includes selectively forming SiO.sub.2 raised features on the first surface relative to the second surface.

Methods of improved selectively for SAM-based selective depositions are described. Some of the methods include forming a SAM on a second surface and a carbonized layer on the first surface. The substrate is exposed to an oxygenating agent to remove the carbonized layer from the first surface, and a film is deposited on the first surface over the protected second surface. Some of the methods include overdosing a SAM molecule to form a SAM layer and SAM agglomerates, depositing a film, removing the agglomerates, reforming the SAM layer and redepositing the film.

A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiN.sub.x monolayer at temperatures below about 300 C.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet chemical metal plating, using an adhesion promotion layer on the layer of molding compound and forming at least one metal layer on the adhesion promotion layer or forming at least one metal layer on the adhesion promotion layer by wet chemical metal plating processes.

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.