An inhibitor for selectively depositing a thin film may include a compound represented by Formula 1 below:

##STR00001##

where, R.sup.1 is an aldehyde group, an amino group, a carbonyl group, a ketone group, a nitrile group, an acyl halide group, a substituted or unsubstituted C2 to C20 alkenyl group, or a substituted or unsubstituted C2 to C20 alkynyl group, R.sup.2 is a halogen atom, a substituted or unsubstituted C1 to C10 alkylhalide group, a substituted or unsubstituted C4 to C10 tertiary alkyl group, or a substituted or unsubstituted C1 to C10 alkylthio group, and n is an integer from 1 to 5. The inhibitor is adsorbed to a surface of a first layer but not adsorbed to a surface of a second layer. The first layer may include a metal-based material, and the second layer is different from the first layer and may include an insulating material.

A method for preparing a microelectronic component includes cleaning of the surface of an exposed layer with a basis of a III-V material by a cyclic plasma treatment, each cycle comprising a purge phase and a plasma treatment phase. During the formation of the plasma, a bias voltage is applied to the substrate. The method further includes depositing, on the cleaned surface, a subsequent layer. The method provides an optimal cleaning of the exposed layer while minimising, and preferably avoiding degradation of the structure. The preparation method thus makes it possible to improve the quality of the interface between the layer with a basis of a III-V material and the subsequent layer. The electrical properties of the component are consequently improved.

A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties.

The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an Al.sub.xY.sub.2-xO.sub.3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, wherein 1.2x1.9. The composite gate dielectric layer modifies the Al/Y ratio of the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, changes the average number of atomic coordination in the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the Al.sub.xY.sub.2-xO.sub.3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Embodiments are directed to a method and resulting structures for improving the adhesion of a polymer to the surface of a substrate. A substrate is formed and a surface of the substrate is modified to include XH functional group terminations. A polymer is formed on the modified surface of the substrate. The polymer and substrate are heated to chemically bond the polymer to the surface of the substrate.

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or SH) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200 C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200 C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

Embodiments are directed to a method and resulting structures for improving the adhesion of a polymer to the surface of a substrate. A substrate is formed and a surface of the substrate is modified to include XH functional group terminations. A polymer is formed on the modified surface of the substrate. The polymer and substrate are heated to chemically bond the polymer to the surface of the substrate.