A method and processing system for integrated in-situ dry surface preparation and area selective film deposition. The method includes providing a substrate having a first film and a second film, the first and second films containing different materials, and performing sequential dry processing steps at sub-atmospheric pressure, the steps including: a) treating the substrate to remove residue from the first and second films, b) exposing the substrate to an oxygen-containing gas to functionalize a surface of the first film, c) exposing the substrate to a reactant gas that selectively forms a blocking layer on the first film or the second film, and d) selectively depositing a material film on the first film or the second film not containing the blocking layer by exposing the substrate to a deposition gas. Steps a)-c) or a)-d) may be performed without exposing the substrate to air at any time.

There is included (a) loading a substrate where a conductive metal-element-containing film is exposed on a surface of the substrate into a process chamber under a first temperature; (b) supplying a reducing gas to the substrate while raising a temperature of the substrate to a second temperature higher than the first temperature in the process chamber; (c) forming a first film on the metal-element-containing film, by supplying a first process gas, which does not include an oxidizing gas, to the substrate under the second temperature in the process chamber; and (d) forming a second film on the first film such that the second film is thicker than the first film, by supplying a second process gas, which includes an oxidizing gas, to the substrate under a third temperature higher than the first temperature in the process chamber.

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Atomic layer deposition processes for forming germanium oxide thin films are provided. In some embodiments the ALD processes can include the following: contacting the substrate with a vapor phase tetravalent Ge precursor such that at most a molecular monolayer of the Ge precursor is formed on the substrate surface; removing excess Ge precursor and reaction by products, if any; contacting the substrate with a vapor phase oxygen precursor that reacts with the Ge precursor on the substrate surface; removing excess oxygen precursor and any gaseous by-products, and repeating the contacting and removing steps until a germanium oxide thin film of the desired thickness has been formed.

A method and apparatus for depositing a material on a surface of a substrate are disclosed. The method can include a treatment step to suppress a rate of material deposition on the surface of the substrate. The method can result in higher-quality deposited material. Additionally or alternatively, the method can be used to fill a recess within the surface of the substrate with reduced or no seam formation.

An insulating layer structure for a semiconductor product. The insulating layer structure includes a device substrate, a supporting substrate and a thin film layer. The device substrate and the supporting substrate are silicon wafers. The thin film layer(s) is/are arranged on the device substrate or/and the supporting substrate. The device substrate and the supporting substrate are bonded together through the thin film layer arranged on at least one of the device substrate and the supporting substrate to form an integral multilayer SOI structure. The insulating layer structure formed by the present invention solves problems of serious spontaneous heating of an existing SOI device, severe warpage of an existing SOI structure caused by high-temperature annealing, a poor radio frequency characteristic and the like, and has a predictable relatively higher economic and social value.

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

A substrate processing method for forming fully self-aligned vias. The method may be performed in a batch processing system that is capable of simultaneously processing multiple substrates, where the batch processing system includes a process chamber containing processing spaces defined around an axis of rotation in the process chamber. Each of the substrates contain a first surface and a second surface, and the method includes selectively forming SiO.sub.2 raised features on the first surface relative to the second surface.