Patent classifications
H01L21/02304
MULTILAYER SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING MULTILAYER SEMICONDUCTOR STRUCTURE
A multilayer semiconductor structure of the present disclosure includes a substrate a buffer layer disposed on the substrate and a semiconductor layer disposed on the buffer layer. A void is provided between the buffer layer and the semiconductor layer.
Semiconductor package with chip end design and trenches to control fillet spreading in stacked chip packages
A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.
Method for manufacturing rutile titanium dioxide layer and semiconductor device including the same
A method for method for manufacturing a rutile titanium dioxide layer according to the inventive concept includes forming a sacrificial layer on a substrate, and depositing a titanium dioxide (TiO.sub.2) material on the sacrificial layer. The sacrificial layer includes a metal oxide of a rutile phase. An amount of oxygen vacancy of the sacrificial layer after depositing the titanium dioxide material is greater than an amount of oxygen vacancy of the sacrificial layer before depositing the titanium dioxide material. The metal oxide includes a metal different from titanium (Ti).
Methods Of Selectively Forming Metal-Containing Films
Methods of forming metal-containing films are provided. The methods include forming a blocking layer, for example, on a first substrate surface, by a first deposition process and forming the metal-containing film, for example, on a second substrate surface, by a second deposition process.
DIELECTRIC THIN-FILM STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME
Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a <hk0>, <h00>, or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.
SELECTIVE DEPOSITION ON METALS USING POROUS LOW-K MATERIALS
A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR
A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 10.sup.21 cm.sup.-3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1 × 10.sup.18 cm.sup.-3 and a carbon concentration at the first position is equal to or less than 1 × 10.sup.18 cm.sup.-3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1 × 10.sup.18 cm-.sup.3.
CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES
Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
COMPOSITION
A composition for temporary bonding, includes: (A) a (meth)acrylate having the following (A-1) and (A-2): (A-1) a monofunctional (meth)acrylate whose side chain is an alkyl group having 18 or more carbon atoms and homopolymer has a Tg of −100° C. to 60° C., and (A-2) a polyfunctional (meth)acrylate; (B) a polyisobutene homopolymer and/or a polyisobutene copolymer; and (C) a photo radical polymerization initiator.
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.