A method for forming a thin film structure may include providing a TiN member, forming a MoO.sub.2 thin film on the TiN member by using a first ALD (atomic layer deposition) process using ozone (O.sub.3) as a reactant, and forming a TiO.sub.2 thin film having a rutile crystal structure on the MoO.sub.2 thin film by using a second ALD process. The MoO.sub.2 thin film may have a thickness of about 10 nm or less. A TiO.sub.2 element layer may be further formed between the TiN member and the MoO.sub.2 thin film. The TiO.sub.2 element layer may have a nanodot array shape or a continuous layer structure. The TiO.sub.2 thin film may have a dielectric constant of 100 or more. The method of manufacturing a capacitor may further include forming a conductive material layer on the TiO.sub.2 thin film.

Methods for void-free SiO.sub.2 filling of fine recessed features and selective SiO.sub.2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO.sub.2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO.sub.2 film until the recessed features are filled with SiO.sub.2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO.sub.2 material form shallow trench isolation (STI) structures in a semiconductor device.

Facilitating throughput in nanoimprint lithography processes by using an imprint resist including fluorinated components and a substrate treated with a pretreatment composition to promote spreading of an imprint resist on the substrate. The interfacial surface energy between the pretreatment composition and air exceeds the interfacial surface energy between the imprint resist and air by at least 1 mN/m, and the contact angle of the imprint resist on the surface of the nanoimprint lithography template is less than 15°.

A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.

A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.

Compositions useful for improving the adhesion of coating compositions, such as dielectric film-forming compositions, include a hydrolyzed poly(alkoxysilane). These compositions are useful in methods of improving the adhesion of coating compositions to a substrate.

An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a substrate, wherein said first layer is a metal oxide adhesion layer selected from the group consisting of an oxide of a Group IIIA metal element, a Group IVB metal element, a Group VB metal element, and combinations thereof; vapor depositing a second layer upon said first layer, wherein said second layer includes a silicon-containing layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; and vapor depositing a third layer upon said second layer, wherein said third layer is a functional organic-comprising layer, wherein said functional organic-comprising layer is a SAM.

An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate insulating layer and the gate electrode are located in a middle position of the semiconductor layer and have a uniform shape and size. In a region on the semiconductor layer that is not covered by the gate insulating layer, there is further provided a metal diffusion layer. A barrier layer includes a portion covering the gate insulating layer and the gate electrode and a portion located around the semiconductor layer. A passivation layer covers the semiconductor layer, the gate insulating layer, the gate electrode and the barrier layer. Source and drain electrodes are connected to the metal diffusion layer respectively, and a pixel electrode contacts with the drain electrode.

A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.